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Original question:

Linux/AM3358: Audio codec initialization issue

Linux/BEAGLEBK: McASP in I2S master mode - clock rate issue (BLCK, WS)

Galen Church
Prodigy 170 points

Part Number: BEAGLEBK

Tool/software: Linux

Hi, I am having an issue with the WS and BCLK rate being produced by my system as running the McASP in I2S master mode.  I am interfacing the Beaglebone Black over I2S with a BT radio. 

When I play the 44.1kHz audio my printk() statements produce the following parameters with good audio and a scoped output to match.

[ 1022.052468] sample_size=16
[ 1022.052482] rate=44100
[ 1022.052493] sysclk=24000000
[ 1022.052496] bclk_freq=1411200

When I play the 8kHz audio my printk() statements produce the following parameters but the audio us speed up and the scoped output does not match the parameters.

[ 1081.128650] sample_size=16
[ 1081.128664] rate=8000
[ 1081.128673] sysclk=24000000
[ 1081.128677] bclk_freq=256000

My scope output produces a BCLK at 827.8kHz (rather then 256kHz) and a WS signal at 25.86kHz (rather then 8kHz).  My guess would be this has to-do with a mis-match in mapping the rates to the clock divider circuitry described in section 22.3.5.1 of spruh73p.pdf.  I am just not sure where to find this mapping inside the linux kernel drivers.  I am using 4.14.40 from the TI sdk and my drivers have been largely taken from the steps in: http://processors.wiki.ti.com/index.php/Sitara_Linux_Audio_DAC_Example.

  • 0
    TI__Guru**** 170625 points
    Hi Galen,

    Do you use BEAGLEBK or custom board that is based on BEAGLEBK?

    Do you use AM335x McASP module in master mode?

    The McASP BCLK and WS are configured in McASP driver:

    linux-4.14.40/sound/soc/davinci/davinci-mcasp.c

    In this driver are configured McASP registers XFMT, AFSXCTL, ACLKXCTL, AHCLKXCTL, etc

    You can also explore below file:

    linux-4.14.40/sound/soc/soc-core.c

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Prodigy 170 points

    Hi Pavel,

    Thank you, soc-core.c looks very useful in finding the issue.  The Beaglebone-Black is stock, then interfaced through P9 to my custom board.  I am using the McASP is in master mode on McASP0.  The device tree is configured as follows:

    	mcasp0_pins: mcasp0_pins {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* MCASP0_ACLKX.mcasp0_aclkx */
			AM33XX_IOPAD(0x9AC, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* MCASP0_AHCLKX.mcasp0_ahclkx*/
			AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* MCASP0_FSX.mcasp0_fsx */
			AM33XX_IOPAD(0x998, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* MCASP0_AXR0.mcasp0_axr0*/
			AM33XX_IOPAD(0x99C, PIN_INPUT_PULLDOWN | MUX_MODE2)	    /* MCASP0_AHCLKR.mcasp0_axr2 */
		>;
	};

    Regards,
    Galen

  • 0 in reply to Galen Church
    TI__Guru**** 170625 points
    Galen,

    You can also refer to the below documents, where McASP clock scheme is explained:

    www.ti.com/.../sprac97.pdf
    www.ti.com/.../sprac09a.pdf
    www.ti.com/.../sprac10.pdf

    Regards,
    Pavel
  • 0 in reply to Pavel Botev
    Prodigy 170 points

    Hi Pavel,

    Thanks for the documents they look very interesting.  I believe I located where the issue is.  My driver along with the example are only setting clock div_id 1 which corresponds to the BCLK which sets ACLKXCRL[4-0].  When I am running at 8kHz the divider is calculated as 93 (0x5D).  When masked out in the function (as this divider is only 1-32) __davinci_mcasp_set_clkdiv() I get 0x1D which corresponds to the rates I see on the scope. 

    I think if I modify my diver to handle not only setting the divider ACLKXCRL[4-0] but also the larger divider AHLKXCTL[11-0] which feeds BCLK it should be able to work with these slower rates.

    Thanks for the help,
    Galen