RTOS/AM5728: AM57x GPMC read access time

Hi,

Check Table 15-522 in the AM572x TRM Rev. J. You can use the bitfields TIMEPARAGRANULARITY and GPMCFCLKDIVIDER to adjust the GPMC timings for slower memories. See also sections 15.4.4.2 and 15.4.4.8.3.1.7

I have already modified the TIMEPARGRANULARITY (GPMC_TIMEPARAGRANULARITY_X2) to obtain 233 ns.
However, GPMCFCLKDIVIDER (DIV by 1 ~ 4) showed no change in timing.

Hi,

The 233ns is obtained by 1/133*31, that is 1/133MHz FCLK * RDACCESSTIME. Why you need to change GPMC_TIMEPARAGRANULARITY from 1 to 2? Also, if you found that GPMCFCLKDIVIDER (1...4) doesn't work. Where do you measure that?

From AM5728 TRM Table 3-232. CD_L3_MAIN1 Modules Clocks Association, L3MAIN1_L3_GICLK is the input to many modules. It is not good to change this clock. We need to understand why GPMCFCLKDIVIDER didn't work.

Regards, Eric

Hi.
We change the GPMC_TIMEPARAGRANULARITY from 1 to 2 because the memory device requires at least 575 ns of read time.
I selected GPMCFCLKDIVIDER through the code below.
GPMCFclkDividerSelect(baseAddr, GPMC_CHIP_SELECT_0, GPMC_FCLK_DIV_BY_4) ;

We changed the value from GPMC_FCLK_DIV_BY_1 to GPMC_FCLK_DIV_BY_4, but the width of read signal (OE) was unchanged.

The signal width of read signal (OE) was measured by the oscilloscope.

How can we get a read time of 575ns?

Below is the full text of the GPMC setting code.

================================================================================================================
#define CS_WR_OFF_TIME 0x1E
#define CS_RD_OFF_TIME 0x1E
#define CS_ON_TIME 0x01
#define ADV_ON_TIME 0x02
#define ADV_RD_OFF_TIME 0x04
#define ADV_WR_OFF_TIME 0x04
#define OE_ON_TIME 0x01
#define OE_OFF_TIME 0x1D
#define WE_ON_TIME 0x0A
#define WE_OFF_TIME 0x19
#define RD_CYCLE_TIME 0x1F
#define WR_CYCLE_TIME 0x1F
#define RD_ACCESS_TIME 0x1D
#define WR_DATA_ON_ADMUX 0x06
#define WR_ACCESS_TIME 0x00
#define CYC2CYC_DELAY 0x05
void GpmcInit()
{
uint32_t retVal = 0;
uint32_t baseAddr = CSL_MPU_GPMC_CONF_REGS_REGS;
uint32_t CsTimingParam, WeOeTimingParams, RdAccTimingParams, Cyc2TimingParams;

GPMCModuleSoftReset(baseAddr) ;

do{
retVal = GPMCModuleResetStatusGet(baseAddr) ;
}while (retVal == 0) ;

/* GPMC Clock set to no idle */
GPMCIdleModeSelect(baseAddr, GPMC_IDLEMODE_NOIDLE);

/* Do not enable Auto Idle for GPMC clock */
GPMCAutoIdleConfig(baseAddr, GPMC_AUTOIDLE_FREERUN);

/* Disable interrupt from GPMC */
GPMCIntDisable(baseAddr, GPMC_FIFOEVENT_INT) ;
GPMCIntDisable(baseAddr, GPMC_TERMINALCOUNT_INT) ;
GPMCIntDisable(baseAddr, GPMC_WAIT0EDGEDETECTION_INT) ;
GPMCIntDisable(baseAddr, GPMC_WAIT1EDGEDETECTION_INT) ;

/* Disable Timout */
GPMCTimeOutFeatureConfig(baseAddr, GPMC_TIMEOUTFEATURE_DISABLE) ;

CsTimingParam = GPMC_CS_TIMING_CONFIG(CS_WR_OFF_TIME, CS_RD_OFF_TIME, GPMC_CS_EXTRA_NODELAY, CS_ON_TIME);
WeOeTimingParams =GPMC_WE_OE_TIMING_CONFIG(WE_OFF_TIME, GPMC_WE_EXTRA_NODELAY, WE_ON_TIME, 0, OE_OFF_TIME, GPMC_OE_EXTRA_NODELAY, 0,OE_ON_TIME );
RdAccTimingParams = GPMC_RDACCESS_CYCLETIME_TIMING_CONFIG(RD_CYCLE_TIME, WR_CYCLE_TIME, RD_ACCESS_TIME, 0 );
Cyc2TimingParams = GPMC_CYCLE2CYCLE_BUSTURNAROUND_TIMING_CONFIG(CYC2CYC_DELAY, GPMC_CYCLE2CYCLESAMECSEN_C2CDELAY, GPMC_CYCLE2CYCLEDIFFCSEN_NOC2CDELAY, 0 );

/* Cs 0 ET1100 */
GPMCDevTypeSelect(baseAddr,GPMC_CHIP_SELECT_0,GPMC_DEVICETYPE_NORLIKE) ;
GPMCAddrDataMuxProtocolSelect(baseAddr, GPMC_CHIP_SELECT_0,GPMC_MUXADDDATA_NOMUX ) ;
GPMCDevSizeSelect(baseAddr, GPMC_CHIP_SELECT_0, GPMC_DEVICESIZE_16BITS ) ;
GPMCDevPageLenSet(baseAddr, GPMC_CHIP_SELECT_0, GPMC_DEV_PAGELENGTH_SIXTEEN);
GPMCTimeParaGranularitySelect(baseAddr, GPMC_CHIP_SELECT_0, GPMC_TIMEPARAGRANULARITY_X1) ;
GPMCFclkDividerSelect(baseAddr, GPMC_CHIP_SELECT_0, GPMC_FCLK_DIV_BY_4) ;
GPMCCSTimingConfig(baseAddr, GPMC_CHIP_SELECT_0, CsTimingParam) ;
GPMCWEAndOETimingConfig(baseAddr, GPMC_CHIP_SELECT_0,WeOeTimingParams);
GPMCRdAccessAndCycleTimeTimingConfig(baseAddr, GPMC_CHIP_SELECT_0,RdAccTimingParams) ;
GPMCWrAccessAndWrDataOnADMUXBusTimingConfig(baseAddr, GPMC_CHIP_SELECT_0, WR_ACCESS_TIME, WR_DATA_ON_ADMUX ) ;
GPMCycle2CycleAndTurnArndTimeTimingConfig(baseAddr, GPMC_CHIP_SELECT_0, Cyc2TimingParams);
GPMCWaitPinMonitoringConfig(baseAddr,GPMC_CHIP_SELECT_0,GPMC_MODE_READ, GPMC_WAITMONITORING_DISABLE) ;
GPMCWaitPinMonitoringConfig(baseAddr,GPMC_CHIP_SELECT_0,GPMC_MODE_WRITE, GPMC_WAITMONITORING_DISABLE) ;

// Map Cs 0 Address beg from 0x04000000 for FPGA Flash.
GPMCCSConfig(baseAddr,GPMC_CHIP_SELECT_0,GPMC_CS_DISABLE) ; // Disable Chip Select First
GPMCMaskAddrSet(baseAddr,GPMC_CHIP_SELECT_0,GPMC_CS_SIZE_16MB ) ; // 16MB is the min size that supported .
GPMCBaseAddrSet(baseAddr,GPMC_CHIP_SELECT_0,(0x04000000 >> 24)) ; // This address is what ROM boot loader set up to.
GPMCCSConfig(baseAddr,GPMC_CHIP_SELECT_0,GPMC_CS_ENABLE) ;
}


================================================================================================================

Hello Eric,
Sangwook Kim would like to interface to ET1100 via GPMC, but current situation is hard to generate over 575nsec.
It can't be achieved the memory access clock speed by only using GPMCFCLKDIVIDER(0~31), so they would like to change upper clock chain, L3MAIN1_L3_GICLK.

Would you please guide them where to add the code.
Or, please provide them the example code for GPMC low speed clock setting.

Best Regard,
Ernest Cho.

Hi.
We found that "GPMCFCLKDIVIDER " generated gpmc_clk instead of reducing GPMC_FCLK.(AM572x TRM - 15.4.4.2)
The maximum read time available at 133 MHz is 233 nsec (31 * (1/133M) = 233 nsec).

In order to obtain 575 nsec, L3MAIN1_L3_GICLK must be reduced.
We're searching for a lot of data, but we haven't found a way to reduce L3MAIN1_L3_GICLK.
How can we reduce it? Please help me.

Regards,
SangWook

Hi,

From Figures 15-51/52/53, the gpmc_clk is the clock to the external memory device. And from 15.4.4.2 The gpmc_clk is generated by the GPMC from the internal GPMC_FCLK clock. The source of the GPMC_FCLK is described in Table 15-447. The gpmc_clk is configured using the GPMC_CONFIG1_i[1:0] GPMCFCLKDIVIDER bit field (where i = 0 to 7), as shown in Table 15-450.

I don't understand why GPMCFCLKDIVIDER doesn't have any effects to reduce the gpmc_clk at 133MHz GPMC_FCLK. If you have to reduce the GPMC_FCLK, as you know the input source for this is L3MAIN1_L3_GICLK, so the L3MAIN1_L3_GICLK needs to be reduced. Let me check how to do this.

Regards, Eric

As Eric has already stated, you do not want to change the L3 clock.  This would adversely affect many other systems.  You must change the GPMC FCLK.  Please focus your debug on this one clock alone.

Tom

Are you trying to boot from this slow memory attached to the GPMC interface or is this a run-time requirement?

Tom

Any update?

Regards, Eric