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Linux/AM5718: PWM issue on AM5718 custom board.

Simit Ghane
Intellectual 980 points
Part Number: AM5718

Tool/software: Linux

Hi All,

We have developed one custom board based on AM5718. We are able to configure PWM successfully for LED. But when we trigger the command for  set the PWM period or Duty Cycle.

We will get the below error.

44000000.ocp:L3 Custom Error: MASTER MPU TARGET L4_PER1_P3 (Idle): Data Access in Supervisor mode during Functional access
[ 305.308519] Modules linked in: dwc3 udc_core usb_common snd_soc_simple_card snd_soc_simple_card_utils leds_gpio snd_soc_omap_hdmi_audio ahci_platform libahci_platform libahci omap_aes_driver libata ti)
[ 305.349843] CPU: 0 PID: 398 Comm: sh Tainted: G W O 4.9.59-g9a257488d4 #419
[ 305.357788] Hardware name: Generic DRA72X (Flattened Device Tree)
[ 305.363902] Backtrace:
[ 305.366365] [<c020b29c>] (dump_backtrace) from [<c020b558>] (show_stack+0x18/0x1c)
[ 305.373963] r7:00000009 r6:600c0193 r5:00000000 r4:c1022668
[ 305.379645] [<c020b540>] (show_stack) from [<c04cd558>] (dump_stack+0x8c/0xa0)
[ 305.386896] [<c04cd4cc>] (dump_stack) from [<c022e3d0>] (__warn+0xec/0x104)
[ 305.393883] r7:00000009 r6:c0bc95bc r5:00000000 r4:ed0cdb68
[ 305.399563] [<c022e2e4>] (__warn) from [<c022e428>] (warn_slowpath_fmt+0x40/0x48)
[ 305.407074] r9:00000006 r8:ec1c8c50 r7:c0bc9428 r6:00000000 r5:c0bc94e8 r4:c0bc958c
[ 305.414849] [<c022e3ec>] (warn_slowpath_fmt) from [<c04fd408>] (l3_interrupt_handler+0x25c/0x36c)
[ 305.423753] r3:ec1c8ac0 r2:c0bc958c
[ 305.427336] r4:80080003
[ 305.429878] [<c04fd1ac>] (l3_interrupt_handler) from [<c027fcf4>] (__handle_irq_event_percpu+0xb4/0x138)
[ 305.439395] r10:c104dd6e r9:ec1cb200 r8:00000017 r7:ed0cdc8c r6:00000000 r5:ec1cb200
[ 305.447253] r4:ec1c8fc0
[ 305.449793] [<c027fc40>] (__handle_irq_event_percpu) from [<c027fd9c>] (handle_irq_event_percpu+0x24/0x60)
[ 305.459483] r10:00000000 r9:ed0cc000 r8:ec006000 r7:00000000 r6:c1008bf4 r5:ec1cb200
[ 305.467341] r4:ec1cb200
[ 305.469882] [<c027fd78>] (handle_irq_event_percpu) from [<c027fe18>] (handle_irq_event+0x40/0x64)
[ 305.478786] r5:ec1cb260 r4:ec1cb200
[ 305.482374] [<c027fdd8>] (handle_irq_event) from [<c02834c8>] (handle_fasteoi_irq+0xc0/0x190)
[ 305.490930] r7:00000000 r6:c1008bf4 r5:ec1cb260 r4:ec1cb200
[ 305.496610] [<c0283408>] (handle_fasteoi_irq) from [<c027ef30>] (generic_handle_irq+0x2c/0x3c)
[ 305.505254] r7:00000000 r6:00000000 r5:00000017 r4:c0e5cde0
[ 305.510933] [<c027ef04>] (generic_handle_irq) from [<c027f4a4>] (__handle_domain_irq+0x64/0xbc)
[ 305.519666] [<c027f440>] (__handle_domain_irq) from [<c02014a0>] (gic_handle_irq+0x40/0x7c)
[ 305.528047] r9:ed0cc000 r8:fa213000 r7:fa212000 r6:ed0cdd48 r5:fa21200c r4:c1003424
[ 305.535820] [<c0201460>] (gic_handle_irq) from [<c020c0f8>] (__irq_svc+0x58/0x8c)
[ 305.543330] Exception stack(0xed0cdd48 to 0xed0cdd90)
[ 305.548399] dd40: ec256e88 600c0013 00000001 0000002d 00000000 00000004
[ 305.556607] dd60: ec256e88 600c0013 0000c350 00000000 00000000 ed0cdda4 ed0cdda8 ed0cdd98
[ 305.564815] dd80: c062f8cc c08d27ec 200c0013 ffffffff
[ 305.569883] r9:ed0cc000 r8:0000c350 r7:ed0cdd7c r6:ffffffff r5:200c0013 r4:c08d27ec
[ 305.577661] [<c08d27c4>] (_raw_spin_unlock_irqrestore) from [<c062f8cc>] (__pm_runtime_idle+0x74/0x88)
[ 305.587006] [<c062f858>] (__pm_runtime_idle) from [<c0229f20>] (omap_dm_timer_disable+0x1c/0x20)
[ 305.595824] r7:ecd6d0a0 r6:0000c350 r5:ecd07b90 r4:ecd07b90
[ 305.601509] [<c0229f04>] (omap_dm_timer_disable) from [<bf020044>] (pwm_omap_dmtimer_start+0x44/0x58 [pwm_omap_dmtimer])
[ 305.612425] [<bf020000>] (pwm_omap_dmtimer_start [pwm_omap_dmtimer]) from [<bf02010c>] (pwm_omap_dmtimer_enable+0x24/0x34 [pwm_omap_dmtimer])
[ 305.625167] r5:ecd07b90 r4:ecd07bb8
[ 305.628758] [<bf0200e8>] (pwm_omap_dmtimer_enable [pwm_omap_dmtimer]) from [<c0514390>] (pwm_apply_state+0x180/0x1bc)
[ 305.639408] r5:ecd6d080 r4:ed0cde38
[ 305.642995] [<c0514210>] (pwm_apply_state) from [<c0514a60>] (enable_store+0x84/0xbc)
[ 305.650854] r9:00000000 r8:00000000 r7:00000002 r6:ecd6d080 r5:ecd671a4 r4:00000000
[ 305.658629] [<c05149dc>] (enable_store) from [<c061ff38>] (dev_attr_store+0x20/0x2c)
[ 305.666399] r7:ed092c80 r6:ed0cdf78 r5:00000002 r4:c05149dc
[ 305.672080] [<c061ff18>] (dev_attr_store) from [<c0397b1c>] (sysfs_kf_write+0x48/0x4c)
[ 305.680025] r5:00000002 r4:c061ff18
[ 305.683611] [<c0397ad4>] (sysfs_kf_write) from [<c03972c8>] (kernfs_fop_write+0xdc/0x1dc)
[ 305.691818] r5:00000002 r4:ecf46280
[ 305.695405] [<c03971ec>] (kernfs_fop_write) from [<c032ee90>] (__vfs_write+0x34/0x120)
[ 305.703351] r10:00000000 r9:00000002 r8:00000000 r7:00000002 r6:ed0cdf78 r5:c03971ec
[ 305.711209] r4:ecaa8e40
[ 305.713750] [<c032ee5c>] (__vfs_write) from [<c032fcdc>] (vfs_write+0xac/0x170)
[ 305.721087] r9:00000002 r8:00000000 r7:ed0cdf78 r6:000d8108 r5:ecaa8e40 r4:00000002
[ 305.728860] [<c032fc30>] (vfs_write) from [<c0330adc>] (SyS_write+0x44/0x98)
[ 305.735933] r9:00000002 r8:000d8108 r7:00000000 r6:00000000 r5:ecaa8e40 r4:ecaa8e40
[ 305.743707] [<c0330a98>] (SyS_write) from [<c0207be0>] (ret_fast_syscall+0x0/0x34)
[ 305.751304] r9:ed0cc000 r8:c0207d84 r7:00000004 r6:b6ef6d58 r5:000d8108 r4:00000002
[ 305.759075] ---[ end trace 82bf4a1b5681e2fe ]---

Will you guys please help me to solve this error.

Thanks,

Simit.

  • 0
    TI__Guru** 100960 points

    Hello Simit,

    * What command are you using to "set the PWM period or Duty Cycle"?
    * What version of Linux are you using?

    Regards,
    Nick

  • 0 in reply to Nick Saulnier
    Intellectual 980 points

    Hi NIck,

     What command are you using to "set the PWM period or Duty Cycle"?

    -> $ echo 1000000000 > /sys/class/pwm/pwmchip4/pwm0/period

        $ echo 1000000000 > /sys/class/pwm/pwmchip4/pwm0/duty_cycle

    What version of Linux are you using?

    -> I am using Linux 4.9.59.

    Thanks,

    Simit

  • 0 in reply to Simit Ghane
    TI__Guru** 100960 points
    Hello Simit,

    Are you observing any issues in functionality? Or is everything working as expected?

    Regards,
    Nick
  • 0 in reply to Nick Saulnier
    TI__Expert 6256 points
    Ref: e2e.ti.com/.../717079 and recommended solutions
    (There are other e2e threads related to debugging L3 noc errors on custom boards , search tool will help)

    Look in TRM on connected modules for L4_PER1 and check differences on device configuration on your custom board (pinmux and DT) .
  • 0 in reply to Simit Ghane
    TI__Guru** 100960 points

    Praneeth brings up a good point. What does your device tree entry look like for the PWM?

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    Intellectual 980 points

    Hi Nick,

    Thanks for the reply.

    Functionality wise i didn't see any problem till now.

    My dts entry is as below.

    timer5: timer@48820000 {
    compatible = "ti,omap5430-timer";
    reg = <0x48820000 0x80>;
    interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
    ti,hwmods = "timer5";
    ti,timer-pwm;
    };

    pwm5: dmtimer-pwm@5 {
    compatible = "ti,omap-dmtimer-pwm";
    ti,timers = <&timer5>;
    #pwm-cells = <3>;
    };

    timer6: timer@48822000 {
    compatible = "ti,omap5430-timer";
    reg = <0x48822000 0x80>;
    interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
    ti,hwmods = "timer6";
    ti,timer-pwm;
    };

    pwm6: dmtimer-pwm@6 {
    compatible = "ti,omap-dmtimer-pwm";
    ti,timers = <&timer6>;
    #pwm-cells = <3>;
    };

    timer7: timer@48824000 {
    compatible = "ti,omap5430-timer";
    reg = <0x48824000 0x80>;
    interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
    ti,hwmods = "timer7";
    ti,timer-pwm;
    };

    pwm7: dmtimer-pwm@7 {
    compatible = "ti,omap-dmtimer-pwm";
    ti,timers = <&timer7>;
    #pwm-cells = <3>;
    };

    timer8: timer@48826000 {
    compatible = "ti,omap5430-timer";
    reg = <0x48826000 0x80>;
    interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
    ti,hwmods = "timer8";
    ti,timer-pwm;
    };

    pwm8: dmtimer-pwm@8 {
    compatible = "ti,omap-dmtimer-pwm";
    ti,timers = <&timer8>;
    #pwm-cells = <3>;
    };

    timer9: timer@4803e000 {
    compatible = "ti,omap5430-timer";
    reg = <0x4803e000 0x80>;
    interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
    ti,hwmods = "timer9";
    ti,timer-pwm;
    };

    pwm9: dmtimer-pwm@9 {
    compatible = "ti,omap-dmtimer-pwm";
    ti,timers = <&timer9>;
    #pwm-cells = <3>;
    };

    timer10: timer@48086000 {
    compatible = "ti,omap5430-timer";
    reg = <0x48086000 0x80>;
    interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
    ti,hwmods = "timer10";
    ti,timer-pwm;
    };

    pwm10: dmtimer-pwm@10 {
    compatible = "ti,omap-dmtimer-pwm";
    ti,timers = <&timer10>;
    #pwm-cells = <3>;
    };

    timer11: timer@48088000 {
    compatible = "ti,omap5430-timer";
    reg = <0x48088000 0x80>;
    interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
    ti,hwmods = "timer11";
    ti,timer-pwm;
    };

    pwm11: dmtimer-pwm@11 {
    compatible = "ti,omap-dmtimer-pwm";
    ti,timers = <&timer11>;
    #pwm-cells = <3>;
    };

    timer12: timer@4ae20000 {
    compatible = "ti,omap5430-timer";
    reg = <0x4ae20000 0x80>;
    interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
    ti,hwmods = "timer12";
    ti,timer-alwon;
    ti,timer-secure;
    ti,timer-pwm;
    };

    pwm12: dmtimer-pwm@12 {
    compatible = "ti,omap-dmtimer-pwm";
    ti,timers = <&timer12>;
    #pwm-cells = <3>;
    };

    Thanks,

    Simit

  • 0 in reply to Simit Ghane
    TI__Guru** 100960 points
    Hello Simit,

    I am sorry for the delay. Are you still working on this problem?

    I am not sure that omap-dmtimer-pwm is the right node to be using in the device tree. Which PWM are you trying to use? The EHRPWM in the PWMSS? The ECAP PWM? Some other PWM?

    Regards,
    Nick
  • 0 in reply to Nick Saulnier
    Intellectual 980 points

    Hello Nick,

    Question: Are you still working on this problem?
    Answer: Yes

    Question:Which PWM are you trying to use? The EHRPWM in the PWMSS? The ECAP PWM? Some other PWM?

    Answer:Actually we need the 8 PWM on our board for our final Application goal and AM5718 has only two hardware PWM. so we need to use the "omap-dmtimer-pwm" timer based PWM for our Application.
    and right now we are getting the correct value on pins but We got some kernel crash report and also we are not getting PWM less the 100 mili second.
    so please help us to change the frequency of 32K to more for getting Micro second PWM Signals.


    Regards,
    Simit

  • 0 in reply to Simit Ghane
    TI__Guru** 100960 points

    Hello Simit,

    Ok, I see. FYI, I am looking at c0wb0y's response in this thread as a reference. Did you include the driver in the kernel config? In menuconfig, Device Drivers ---> <*> Pulse Width Modulation(PWM) Support ---> <*> OMAP Dual-Mode Timer PWM support

    On the question of changing the clock source, take a look at Documentation/devicetree/bindings/pwm/pwm-omap-dmtimer.txt It looks like there is an optional property ti,clock-source that you can change. 

  • 0 in reply to Nick Saulnier
    TI__Guru** 100960 points
    Hello Simit,

    I am sorry that TI responses on this thread were so delayed. Future replies here or on any TI thread will be faster.

    I am marking this thread resolved on my end. If you have any more questions, please reply here or create a new thread.

    Regards,
    Nick
  • 0 in reply to Nick Saulnier
    Intellectual 980 points

    Hi Nick,

    Thanks for the reply.

    Yes I have configure all the sttings that you have mentioned above.and also verified it.

    Now will you please guide us for which clock-source we need to change?

    Thanks,

    Simit

  • 0 in reply to Simit Ghane
    TI__Guru** 100960 points
    Hello Simit,

    I am guessing that the L3 error you were seeing at the beginning of this thread has been resolved. If not, let me know.

    I would use ti,clock-source = 0x01 to use the 32-kHz always-on clock (timer_32k_ck)

    Regards,
    Nick
  • 0 in reply to Nick Saulnier
    Intellectual 980 points

    Hello Nick,

    Still we have same issue of error log because we still haven't changed anything in kernel regarind pwm.

    And yes offcaurse we are using same clock-source that you used but we want to increase the frequency more then 32KHz so which clock-source i need to use.

    Thanks,

    Simit

  • 0 in reply to Simit Ghane
    Intellectual 980 points
    Hello Nick,

    This is just a Gentle reminder.

    Thanks,
    Simit
  • 0 in reply to Simit Ghane
    TI__Guru** 100960 points

    Hello Simit,

    I am currently on vacation for Christmas. I'll respond in early January.

    I misread your initial clock question, I thought you wanted to change your clock source to the 32kHz clock, not another clock in the system.

    This thread has stretched for a long time, and I am not clear on exactly what you are currently working on. You can help me by summarizing your current errors that you want addressed in this thread. Include anything useful like terminal output, unexpected behavior and the inputs/outputs that go with the unexpected behavior, etc. Details about things you have tried and what happened when you tried them would also be useful.

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    TI__Guru** 100960 points
    Hello Simit,

    I am back. It looks like you only have two clock options, the system clock or the 32-kHz clock. From the AM571x Technical reference manual, Timers chapter:

    Each timer (except TIMER12) can be clocked from the system clock (19.2, 20, or 27 MHz) or the 32-kHz
    clock. The selection of clock source is made at the power, reset, and clock management (PRCM) module
    level. TIMER12 can be clocked only from the internal oscillator (on-die oscillator). For more information,
    see Section 3.6.3.1, PRM Clock Source.

    Regards,
    Nick