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RTOS/AM6548: Cache coherency

Kaka
Guru 24520 points
Part Number: AM6548


Tool/software: TI-RTOS

Hi TI Experts,

Please let me confirm the following question.

[Question.1-1]
Can AM65x set the write-back for cache?
[Question.1-2]
Can AM65x support the sharing data between Cortex-A53 and BUS Master IPs like PCIe, EDMA, Ethernet and so on with enabling the cache and write-back mode via SDRAM or on-chip RAM?
[Question1-3]
Can AM65x stay in the cache coherency with above situations??

[Question1-4]
If AM65x support the above case, can the BUS master IPs read the correct data on cache in following case?

1. Write the data to sharing memory region by Cortex-A53
2. This value is on cache (Not reflect on actually memory yet)
3. Access the same memory region by PCIe.
-> At this time, can PCIe read the write back data on cache?

[Question.2-1]
Can AM65x support the sharing data between Cortex-R5 and BUS Master IPs like PCIe, EDMA, Ethernet and so on with enabling the cache and write-back mode via SDRAM or on-chip RAM?

[Question2-2]
Can AM65x stay in the cache coherency with above situations??

[Question2-3]
If AM65x support the above case, can the Bus Master or other cores read the correct data on cache in following case?

1. Write the data to sharing memory region by Cortex-R5
2. This value is on cache (Not reflect on actually memory yet)
3. Access the same memory region by PCIe.
-> At this time, can PCIe read the write back data on cache?

If you have any qeustions, please let me know.
Best regards.
Kaka

  • 0
    TI__Guru** 116770 points

    Kaka,

    Cache write back is supported on A53 and R5F. Check the A53 and R5F TRM for details on Cache Write back feature.

    http://infocenter.arm.com/help/topic/com.arm.doc.ddi0500d/DDI0500D_cortex_a53_r0p2_trm.pdf

    http://infocenter.arm.com/help/topic/com.arm.doc.ddi0460c/DDI0460C_cortexr5_trm.pdf 

    Sharing data between A53 and other Bus master IPs is supported however there is a note in the data manual that indicates that PCIe subsystem doesn`t support addressing modes other than incremental for burst transactions as a result the PCIE addresses cannot be in cacheable memory space.

    For R5F, we have only L1 cache and there is no L2 cache on the device.so for cache coherency look at section 3.4 for different use cases. 

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Guru 24520 points
    Hi Rahul,

    Thank you for your response. I understand that PCIe did not support the addressing mode.
    So, would you please answer for the following questions?( (I changed the bus master from PCIe to R5F or A53)

    [Question1-4]
    If AM65x support the above case, can the BUS master IPs read the correct data on cache in following case?

    1. Write the data to sharing memory region by Cortex-A53
    2. This value is on cache (Not reflect on actually memory yet)
    3. Access the same memory region by R5F.
    -> At this time, can R5F read the write back data on cache?

    [Question2-3]
    If AM65x support the above case, can the Bus Master or other cores read the correct data on cache in following case?

    1. Write the data to sharing memory region by Cortex-R5
    2. This value is on cache (Not reflect on actually memory yet)
    3. Access the same memory region by A53.
    -> At this time, can A53 read the write back data on cache?

    Best regards.
    Kaka
  • 0 in reply to Kaka
    TI__Guru** 116770 points
    Kaka,

    I had also reached out to our systems team for this issue and I would also like to share their response on these questions:

    Short version is AM65x is IO coherent with A53 caches, so traffic from any peripheral or R5 into MSMC SRAM and DDR is kept coherent with A53 caches. For R5 there is no IO coherency for L1D, it needs to be SW managed. Cache allocation policy is orthogonal to coherency, and for PCIe it is unnecessary to go into our SoC bus transactions, PCIe does not support cache coherency for memory on the remote side of the link.

    [Question 1-1 and 2-1]
    TRM is the best reference for cache write-back setting for ARM MMU/MPU regions.


    [Question 1-2]
    Yes enabling cache coherency for all traffic to and from MSMC SRAM and DDR memory for data sharing between A53 and other masters like DMA, Ethernet, PCIe, R5F is supported. R5F does not support cache coherency, L1D must be SW managed for consistency, or shared data must be in the TCM memory. Memory at a remote device mapped over PCIe cannot be cached locally

    [Question 1-3]
    Yes for data written and read from MSMC SRAM and DDR for A53 for the situations that you described in your original post.

    Question [1-4]
    Yes as long as the data is in MSMC SRAM or DDR. PCIe read will snoop the most recent data as long as the memory page/region is marked outer shared and cacheable in MMU and NBSS registers.

    Hope this helps.

    Regards,
    Rahul