Hello!
At very large I see a concept that CPU Core, EDMA3 controller and PCIe subsystem are interconnected through TeraNet switch. There are some references about request priorities of different parties. Honestly, I have no idea how do I decipher those references, so asking for help.
My particular interest in request priority of CPU Core versus EDMA3 controller, when they both compete for PCIe subsystem. Imagine, EDMA3 is making huge DMA transfer. EDMA is breaking either read or write request into smaller blocks and submits to PCIe. What if CPU is making memory read from PCIe data window during this process? PCIe subsystem must issue read request to remote party. So my question is: will this read request from CPU be processed before EDMA initiated requests? Can I control that?
Thanks in advance.
