CCS/TMS320C6678: Why does C6678's tsip only transmit and receive data with link 0?

xiangran sun

Part Number: TMS320C6678

Tool/software: Code Composer Studio

I plan to use c6678's tsip. While I study the example from pdk, I find that only link0 of tsip port0 worked for transmission and reception. I used the example is from "pdk_C6678_1_1_2_6\packages\ti\drv\exampleProjects\TSIP_exampleProject", and only modified several parameters:

cfg->testMode = FALSE;

I think this example should work under active 4 links. But the experiment result is that only one link works.

Please can someone help me with this problem.

over 6 years ago

0 lding over 6 years ago

TI__Guru* 95265 points

Hi,

We have some test example enhancement for this:

•1st goal of this project was to enable all 8 lanes

•2nd goal was to help future customers adjust:

–Number of lanes

–Number of time slots

–Number of ports

•Currently, there are two test projects for TSIP in PDK 1.1.2.6

–TSIP_exampleProject

–TSIP_testProject

•TSIP_testProject is more configurable and was used by the customer

•Current test code can:

–Adjust number of ports

–Adjust number of timeslots

•Current test code cannot:

–Run on more than one lane

–Pass valid data using more than one core

–Use more than 64 timeslots across both ports

Code changes:

•test.c – Three major changes:

1.Timeslot Configuration

•Maximum number of timeslots now dependent on max timeslots AND number of ports

–Previously only dependent on max timeslots

–No need to change max timeslots constant in TSIP.h

•Data sampling clock now doubled previous speed

–With single speed errors were produced

•Data rate can now be changed easily to activate up to 2,4, or 8 lanes

–Previously set to 4 lanes (16Mbps)

2.Lane number

•Each timeslot is now associated with a lane number other than 0

–Previously this could not be adjusted

–Each lane number depends on which core is calling the code

–This makes it possible to run all 1024 timeslots across the 8 lanes/cores

•

3.Interrupt vector

•Previously only had vectorID 7 and 8 for each port respectively

•Having all cores on one vector ID created problems

•VectorID 8 caused problems

•Now cores are split up between vectorID 7 and 9

•test.h

1.Buffer size reduced from 40x22 to 40x8

•This allows more timeslots to fit inside LL2

2.Added section where user can adjust the number of active lanes

•This adjusts the data rate in timeslot configuration section

3.Added error detection for when user uses lane values other than 2,4, or 8

See attached code for your reference, Note this is not part of standard TI release. 7571.enhanced test files.zip

Regards, Eric

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CCS/TMS320C6678: Why does C6678's tsip only transmit and receive data with link 0?