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AM5728: Generating GPMC burst access from ARM core

Koichiro Tashiro
Mastermind 22945 points

Part Number: AM5728

Hi,

Is there any way to generate GPMC burst access from ARM core?
Suppose GPMC is properly configured to handle burst accesses.

I knew;
- using DMA burst accesses
- ARM cache line fill
- LDM/STM instructions
are handled as burst at GPMC.


Are there any other ARM instruction(s) which can generate burst on GPMC?


Thanks and regards,
KoT

  • 0
    TI__Guru**** 161600 points
    Hi KoT,

    Check sections 15.4.4.10.4 Page and Burst Support & 15.4.4.10.5 System Burst vs External Device Burst Support from the TRM to see how burst is supported on AM5728. When configured properly, the GPMC can read/write multiple to external memories or devices (such as FPGA for example).

    You are correct about using dma burst accesses, however I am not aware of LDM/STM instructions & arm cache line fill, these are arm instructions, I am not certain how those use GPMC interface...

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Mastermind 22945 points

    Hi Yordan,

    The TRM section you mentioned just explains how system generated burst is handled at GPMC.
    My question is whether user can generate “system burst” with ARM instruction or not.

    I think someone in TI should answer this kinds of question.

    Thanks and regards,
    KoT

  • 0 in reply to Koichiro Tashiro
    TI__Mastermind 30380 points
    Hi Tashiro-san,

    I am able to generate 2-word bursts with 32-bit (and 64-bit) CPU writes. The GPMC ATTACHEDDEVICEPAGELENGTH is configured for device page (burst) length = 0x2: 16 words.

    volatile uint32_t * GPMC0_32 = (volatile uint32_t*) 0x08000000;
    ...
    *GPMC0_32 = 0x00000002;

    ldr r3, [r11, #-0x40]
    mov r2, #2
    str r2, [r3] ; generates a single 2-word burst (32-bit write across 16-bit GPMC becomes 2-word burst)


    However 64-bit writes come out as two 2-word bursts.

    *GPMC0_64 = 0x0000000000000002;
    ldr r1, [r11, #-0x44]
    mov r2, #2
    mov r3, #0
    strd r2, r3, [r1] ; generates two 2-word bursts (64-bit write across 16-bit GPMC becomes two 2-word bursts, not a 4-word burst)


    Even when I use the below STM assembly, the GPMC splits the accesses into 8 2-word bursts.

    asm(" mov r1, #0x8000000 ");
    asm(" MOV r2, #0x10 ");
    asm(" mov r4, #2 ");
    asm(" mov r5, #0 ");
    asm(" mov r6, #2 ");
    asm(" mov r7, #0 ");
    asm(" mov r8, #2 ");
    asm(" mov r9, #0 ");
    asm(" mov r10, #2 ");
    asm(" mov r11, #0 ");
    asm(" STM r1!, {r4-r11} ");

    I'm not an ARM assembly expert, but the only way I have been able to get a 16-word burst is to use the DMA.

    I'll forward this thread to someone who may know more about ARM instructions and the internals of the device. Perhaps they can recommend another way to generate a burst greater than two words without DMA.

    Regards,
    Mark
  • 0 in reply to Mark M
    TI__Mastermind 30380 points
    Hi Tashiro-san,

    The MMU may be preventing bursts longer than 2 words in my experiments above.

    The GPMC address space is being mapped through the ARM MMU, which may not be allowing the larger burst sizes. I will work with a colleague using a TRACE32 (Lauterbach) to capture what is being sent through the system, and to see if I an get larger bursts with CPU writes, LDM/STM instructions and possibly cache operations.

    I'd like to close this thread for now, and reopen/unlock it when I get some results next week. Use the ask a related question or email me if this thread gets locked.

    Regards,
    Mark