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AM3358: ADC_CLK spec change

shigehiro tsuda
Mastermind 9490 points

Part Number: AM3358

Hi,

The following has been added in rev.K of the latest AM335x datasheet.
Could you tell me why it was added?
Is ADC_CLK unusable at 3MHz or more (described as support up to 24MHz in TRM)?

Table 5-16. TSC_ADC Electrical Parameters
ADC clock frequency  MAX 3MHz

Best Regards,
Shigehiro Tsuda

  • 0
    TI__Guru 63875 points

    The maximum frequency parameter defined in the data sheet is the post-divided ADC clock which is used by the ADC FSM. A pre-divided clock is what is described in the TRM.

     

    The TRM reference to 24MHz and the note attached to it is trying to explain how the pre-divided clock frequency of 24MHz produces the highest sample rate since this is the only pre-divided frequency that can be used to generate the maximum post-divided clock frequency of 3MHz without going over this limit. A 3MHz post-divided ADC clock yields the maximum sample rate of 200kSPS since it takes 15 cycles of the post-divided ADC clock. Any of the other valid pre-divided clock frequencies of 19.2MHz, 25MHz, or 26MHz would not yield the maximum sample rate.

     

    Regards,

    Paul

  • 0 in reply to peaves
    Mastermind 9490 points

    Hi Paul,

    Thank you for quick reply.

    The datasheet of AM335x is added with Max ADC_CLK 3MHz when updated from Rev.J to Rev.K.
    We are concerned about the influence on our customers who heve been already mass-produced and used ADC_CLK at 3MHz or more.

    Is there any detailed information on why it was added when updated Rev.K.?
    Have you found a bug in the hardware of the AM335x and changed it?

    Best Regards,
    Shigehiro Tsuda

  • 0 in reply to shigehiro tsuda
    TI__Guru 63875 points

    The maximum sample rate has always been defined as 200kSPS. This maximum sample rate is achieved when using a post-divided clock frequency of 3MHz since it takes 15 post-divided clock cycles to perform a measurement. So the maximum post-divided clock frequency has always been 3MHz.

    This change was made becasue there was a typographical error in the data sheet where this limit was listed as a typical value rather than a maximum value. We simply moved the value from typical to maximum.

    Regards,
    Paul

  • 0 in reply to peaves
    Mastermind 9490 points
    Hi Paul,

    Thank you for quick reply.

    Where are the following descriptions written in the old datasheet or TRM?
    "The maximum sample rate has always been defined as 200kSPS"
    In the old datasheet, there is a description of NOM 200ksps when ADC_CLK= 3MHz, but MAX and Min values are not defined.

    Best Regards,
    Shigehiro Tsuda
  • 0 in reply to shigehiro tsuda
    TI__Guru 63875 points

    The data sheet feature list describes the ADC as a 12-Bit Successive Approximation Register (SAR) ADC that supports 200K Samples per Second.

    The "Sampling rate" and "ADC clock frequency" values should have been published as a maximum value rather than a nominal value.

    The sampling rate vs ADC clock cycles is described in the AFE functional description provided in the Touchscreen Controller chapter of the TRM.

    Regards,
    Paul

  • 0 in reply to peaves
    Mastermind 9490 points

    Hi Paul,

    Thank you for quick reply.

    As a specification of the ADC clock, I understood that MAX ADC clock 3MHz (sampling rate 200Ksps) from the beginning.

    In the threads below, the ADC clock rate seems to be answering max 24MHz.
    e2e.ti.com/.../1349287

    TRM also did not mention that the ADC clock is max 3MHz and the ADC sampling rate is max 200Ksps.
    The setting of ADC_ClkDiv is up to software.
    In the case of max 3MHz as the clock of the ADC, I think it would be better if you mention it as a restriction on TRM.

    Best Regards,
    Shigehiro Tsuda

  • 0 in reply to shigehiro tsuda
    TI__Guru 63875 points
    Biser did not provide the correct answer for the question you referenced above.

    We need to get the post unlocked and reply with a correction.

    Regards,
    Paul
  • 0 in reply to peaves
    Mastermind 9490 points

    Hi Paul,

    Thank you for quick reply.
    I understood that the answer at this e2e was incorrect.

    Best Regards,
    Shigehiro Tsuda