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66AK2H12: Bus priority

Kz777
Expert 7895 points

Part Number: 66AK2H12

Hi Champs,

We didn't find these two  peripheral bus priority change.

*USB Bus priority

*NETCP Bus priority.

Are these able to change bus priority ?

We found another bus priority register (i.e.EDMA,SRIO)

However, we didn't find those USB and NETCP bus priority register.

Regards,

Kaz

  • 0
    TI__Guru* 95265 points
    Hi,

    You may look at the Wiki: processors.wiki.ti.com/.../Keystone_SoC_Level_Optimizations and Corepac documents www.ti.com/.../sprugw0c.pdf SECTION 8.

    Regards, Eric
  • 0 in reply to lding
    TI__Expert 7895 points

    Hi Eric,

    Thanks.

    We still un-clear about USB and NETCP bus priority.

    Could you please these two bus priority register ?

    If you don't control it, could you please tell us these two default priority number ?

    Regards,

    Kz777

  • 0 in reply to Kz777
    TI__Expert 7895 points
    Hi Eric ,
    We understand NETCP use "PKTDMA". So, we can set priori ty for PKTDMA.

    However, I don't understand how to set priority for USB.
    Could you please check how to set USB priority ?
  • 0 in reply to Kz777
    TI__Guru* 95265 points
    Hi,

    Sorry for the late response! In Keystone 1 and Keystone 2 device, we only add chip level MMR to manipulate the priority for the master interface if that IP does not provide priority information. For USB, the priority is driven internally inside USB subsystem. There are some DWC USB MMR registers control over this.

    The SOC level priority arbitrate the master access the VBUS level, we don’t think VBUS bus priority will make much of a difference. There is not that many places in the interconnect where it would play a part.

    DDR class of service, based on master IDs should have a visible effect. If the USB xhci DMA move data using DDR and other peripherals also use DDR. This is explained in 2.6.4 Class of Service of www.ti.com/.../spruhn7c.pdf. There are two classes available.

    I’d ask for a little bit more on the goal of the setting, are they seeing USB traffic disturbing some realtime and want to limit USB, or do they want better USB throughput?

    Also, there is no K2H USB RTOS driver. How you plan to run USB and what are your overall concerns about priority of different masters?

    Regards, Eric
  • 0 in reply to lding
    TI__Guru* 95265 points
    Kaz,

    I am closing this thread. Please open a new one when you have the system level info what their priority issues of different masters.

    Regards, Eric
  • 0 in reply to lding
    TI__Expert 7895 points

    Hi Eric,


    Sure. I am checking now your question. If we ahve additional, I will run another thread.

    I appreciate your support.

  • 0 in reply to lding
    TI__Expert 7895 points
    Hi Eric,
    >I’d ask for a little bit more on the goal of the setting, are they seeing USB traffic disturbing some realtime and want to limit USB, or do they want >better USB throughput?
    >Also, there is no K2H USB RTOS driver. How you plan to run USB and what are your overall concerns about priority of different masters?
    -They will make their own driver and OS that is similar to RTOS. So, they would like to know if USB has priority setting or not.
    They couldn't find "DWC USB MMR registers " Where do you have this register ?
  • 0 in reply to Kz777
    TI__Guru* 95265 points
    Hi Kaz,

    Thanks for the info! Those DWC USB registers are not documented in TI K2G TRM. Did customer have a NDA with TI before and have a copy of DWC USB 3.0 data book?

    Regards, Eric
  • 0 in reply to lding
    TI__Expert 7895 points
    Hi Eric,
    Sorry for my late reply. We have NDA. However, we don't think they have special USB IP particular NDA.
    If we don't have this NDA, we can't access USP core and we can't set USB bus priority , right ?
  • 0 in reply to Kz777
    TI__Guru* 95265 points
    Kaz,

    You need a USB core document for this USB bus priority setting or develop your own USB driver on K2H. This document is under NDA. Please start a NDA process if needed.

    Regards, Eric