RTOS/TDA2PXEVM: I want to change DDR memory map form 1GB to 2GB

Hi,

Can you try to connect to all CPUs using CCS (make sure configuration has no gel) and see their states.
You might need to load symbols to identify the CPU that has crashed.

Regards,
Rishabh

Hi,

I haven't heard back from you, I'm assuming you were able to resolve your issue.
If not, just post a reply below (or create a new thread if the thread has locked due to time-out).

Regards,
Rishabh

Hi,

Our company system has blocked file updates.
So, I would like to receive a guide from the Vision SDK that changed the DDR memory map from 512MB to 2GB.

Regards,
kyungtae

Hi,

I am not asking for file updates. You can check for CPU states using CCS.
Also did you update vpsLibInitPrms.isAddrTransReq to FALSE for changing the memory map to 2 GB?

Regards,
Rishabh

Hi,

I am sorry. I misunderstood your comment.
I set isAddrTransReq to FALSE in the file below.
vision_sdk/links_fw/src/rtos/links_ipu/system/system_bsp_init.c

290 line
/* This one to one mapping is required for the 1GB builds */
vpsInitPrms.virtBaseAddr = 0x80000000U;
vpsInitPrms.physBaseAddr = 0x80000000U;
vpsInitPrms.isAddrTransReq = FALSE;

Thanks

Regards,
kyungtae

Hi,

Can you please update on the state of different CPUs in order to progress on this issue.
Also did the VPS change have any effect on the boot?

Regards,
Rishabh

Hi,

1. Can you please update on the state of different CPUs in order to progress on this issue.

- CortexA15_0 is follows.

main_common_a15_0.c(168 line, BIOS start())-->system_common.c(752 line, memset(&gSystem_objCommon, 0, sizeof(gSystem_objCommon));)

-> system_ipc_bios_ipc.c(474 line)

Void System_ipcStart(void)
{
    Int32 status = Ipc_S_SUCCESS;

    do
    {
        status = Ipc_start();
    } while (status != Ipc_S_SUCCESS);   ---> this point hang

    /* In case of fast boot System_ipcStart() will be called late,
     * after all cores are up & Notify_registerEvent is not called
     * under System_ipcNotifyInit(), so needs to be called here.
     */
    if(ti_sdo_ipc_Ipc_procSync == ti_sdo_ipc_Ipc_ProcSync_ALL)
    {
        System_ipcNotifyRegister();
    }
}

IPC.c(698 line)

    /* Check whether Ipc_start has been called.  If so, succeed. */
    if (Ipc_module->ipcSharedAddr != NULL) {
        return (Ipc_S_ALREADYSETUP);
    }

- M4_IPU1_C0 is follows.

ti_sysbios_family_arm_m3_Hwi_excHandler_I -> ti_sysbios_family_arm_m3_Hwi_excHandlerMax_I -> ti_sysbios_BIOS_exitFunc_I

-> xdc_runtime_System_exit_E -> exit -> abort

- M4_IPU1_C1 is follows.

main_ipu1_1.c

- M4_IPU2_C0 is follows.

ti_sysbios_BIOS_errorRaiseHook_I -> Utils_commonErrorRaiseHook -> vpsprint -> RemoteLog_serverPustring

2. Also did the VPS change have any effect on the boot?

Sorry, I don't know.

Regards,

kyungtae

Hi,

Can you check the board schematics to make sure that you have indeed got 1 GB memory each connected on EMIF1 and EMIF2 port.

Regards,
Rishabh

Hi,

I check the board schematics. our schematics two MT41K256M16TW in EMIF1 and two MT41K256M16TW in EMIF2.

Thanks.

Regards,
kyungtae

Hi,

1. vision_sdk/apps/build/tda2px/mem_segment_definition_bios.xs

/*
 *******************************************************************************
 *
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 * ALL RIGHTS RESERVED
 *
 *******************************************************************************
 */

/*
 *  ======== mem_segment_definition.xs ========
 *  ======== Single file for the memory map configuration of all cores =========
 */

function getMemSegmentDefinition_external(core)
{
    KB=1024;
    MB=KB*KB;

    DDR3_ADDR                   = 0x80000000;
    DDR3_SIZE                   = (1024+1024)*MB;

    /*
     * In case of ECC_FFI_INCLUDE, DDR3_BASE_ADDR_1 and DDR3_BASE_SIZE_1
     * are hard-coded in as values of gIpcNonCachedDataAddr and
     * gIpcNonCachedDataSize in Ipu1_0.cfg
     * If this DDR3_BASE_SIZE_0 is changed, update  Ipu1_0.cfg
     */
    DDR3_BASE_ADDR_0            = DDR3_ADDR;
    DDR3_BASE_SIZE_0            = 1024*MB;

    /* The start address of the second mem section should be 16MB aligned.
     * This alignment is a must as a single 16MB mapping is used for EVE
     * to map SR0, REMOTE_LOG_MEM sections.
     * tlb_config_eveX.c need to be modified otherwise
     */
    DDR3_BASE_ADDR_1            = DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0;
    DDR3_BASE_SIZE_1            = DDR3_SIZE - DDR3_BASE_SIZE_0;
    if(core=="ipu1_1" || core=="ipu1_0" || core=="ipu2" || core=="a15_0")
    {
        /*  for ipu1_0, ipu1_1, ipu2 DDR3_BASE_ADDR_1 should be
         *  in non-cached virtual address of
         *  DDR3_BASE_ADDR_1 + 512*MB
         */
/*        DDR3_BASE_ADDR_1        = DDR3_BASE_ADDR_1+512*MB; */
    }

    DSP1_L2_SRAM_ADDR           = 0x40800000;
    DSP1_L2_SRAM_SIZE           = 288*KB;

    DSP2_L2_SRAM_ADDR           = 0x41000000;
    DSP2_L2_SRAM_SIZE           = 288*KB;

    EVE1_SRAM_ADDR              = 0x42000000;
    EVE1_SRAM_SIZE              = 1*MB;

    EVE2_SRAM_ADDR              = 0x42100000;
    EVE2_SRAM_SIZE              = 1*MB;

    TOTAL_MEM_SIZE              = (DDR3_SIZE);

    /* First 512 MB - cached */
    /* EVE vecs space should be align with 16MB boundary, and if possible try to fit
     * the entire vecs+code+data in 16MB section. In this case a single TLB map would
     * be enough to map vecs+code+data of an EVE.
     * tlb_config_eveX.c need to be modified if any of these EVE memory sections or
     * SR1_FRAME_BUFFER_MEM section is modified.
     */

    /* EVE self-branch instruction block - EVE1_VECS
     * In SBL, EVE self-branch instruction is inserted @ 0x80000000 if no AppImage for EVE.
     * This could overwrites the code/data loaded at 0x80000000.
     * So Reserving a small memory block in the beginning of the DDR @0x8000 0000 for
     * EVE self-branch instruction if no AppImage for EVE.
     * If EVE enabled, then the EVE VECS/DATA/CODE is placed @0x8000 0000,
     * and hence we did not observe any issue.
     * If EVE is disabled, then also DO NOT remove this EVE1_VECS section @0x80000000,
     * if no AppImage for EVE. This could overwrites the code/data loaded at 0x80000000
     */

    EVE1_VECS_SIZE              = 0.5*MB;
    EVE1_CODE_SIZE              =   2*MB;
    EVE1_DATA_SIZE              =13.5*MB;
    EVE2_VECS_SIZE              = 0.5*MB;
    EVE2_CODE_SIZE              =   2*MB;
    EVE2_DATA_SIZE              =13.5*MB;
    NDK_DATA_SIZE               =   4*MB;
    IPU1_1_CODE_SIZE            =   2*MB;
    IPU1_1_DATA_SIZE            =   9*MB;
    IPU1_0_CODE_SIZE            =  12*MB;
    IPU1_0_DATA_SIZE            =  17*MB;
    IPU2_CODE_SIZE              =   2*MB;
    IPU2_DATA_SIZE              =   9*MB;
    DSP1_CODE_SIZE              =   4*MB;
    DSP1_DATA_SIZE              =  12.5*MB;
    DSP1_DATA_SIZE_2            =   1*MB;
    DSP2_CODE_SIZE              =   2*MB;
    DSP2_DATA_SIZE              =  12.5*MB;
    DSP2_DATA_SIZE_2            =   1*MB;
    /* A15_0_CODE_SIZE reduced since it is not used in .bld file.
     * Check .bld for details. Originally 2 + 14 MB.
     */
    A15_0_DATA_SIZE             =  13*MB;
    if(java.lang.System.getenv("OPENCL_INCLUDE") == "yes")
    {
        A15_0_DATA_SIZE_INC     =  101*MB /* in MB */
        A15_0_DATA_SIZE         =  (A15_0_DATA_SIZE + A15_0_DATA_SIZE_INC);
    }

    if(java.lang.System.getenv("ECC_FFI_INCLUDE")=="yes")
    {
        /* Ensure ECC regions are 64kB aligned */
        SR1_FRAME_BUFFER_SIZE       = 309*MB;
        SR1_BUFF_ECC_ASIL_SIZE      =   1*MB;
        SR1_BUFF_ECC_QM_SIZE        =  40*MB;
        SR1_BUFF_NON_ECC_ASIL_SIZE  =   1*MB;
    }
    else
    {
        SR1_BUFF_ECC_ASIL_SIZE      =   4*KB;
        SR1_BUFF_ECC_QM_SIZE        =   4*KB;
        SR1_BUFF_NON_ECC_ASIL_SIZE  =   4*KB;
        SR1_FRAME_BUFFER_SIZE       = 351*MB - (SR1_BUFF_ECC_ASIL_SIZE + SR1_BUFF_ECC_QM_SIZE + SR1_BUFF_NON_ECC_ASIL_SIZE);
        if(java.lang.System.getenv("OPENCL_INCLUDE") == "yes")
        {
            SR1_FRAME_BUFFER_SIZE   = SR1_FRAME_BUFFER_SIZE - A15_0_DATA_SIZE_INC;
        }
    }

    /* Second 512 MB - non-cached */
    /* The start address of the second mem section should be 16MB aligned.
     * This alignment is a must as a single 16MB mapping is used for EVE
     * to map SR0, REMOTE_LOG_MEM sections.
     * tlb_config_eveX.c need to be modified otherwise
     */
    REMOTE_LOG_SIZE             =  160*KB;
    SYSTEM_IPC_SHM_SIZE         =  480*KB;
    LINK_STATS_SIZE             =  256*KB;
    HDVPSS_DESC_SIZE            = 1024*KB;
    SR0_SIZE                    =  128*KB;
    OPENVX_SHM_SIZE             =    2*MB;

    if((java.lang.System.getenv("OPENCL_INCLUDE") == "yes"))
    {
        /* when OpenCL is enabled we need more SR0 space
         */
        SR0_SIZE                =  2*MB;
    }

    /* Cached Section */
    /* EVE vecs space should be align with 16MB boundary, and if possible try to fit
     * the entire vecs+code+data in 16MB section. In this case a single TLB map would
     * be enough to map vecs+code+data of an EVE.
     * tlb_config_eveX.c need to be modified if any of these EVE memory sections or
     * SR1_FRAME_BUFFER_MEM section is modified.
     */

    /* EVE self-branch instruction block - EVE1_VECS
     * In SBL, EVE self-branch instruction is inserted @ 0x80000000 if no AppImage for EVE.
     * This could overwrites the code/data loaded at 0x80000000.
     * So Reserving a small memory block in the beginning of the DDR @0x8000 0000 for
     * EVE self-branch instruction if no AppImage for EVE.
     * If EVE enabled, then the EVE VECS/DATA/CODE is placed @0x8000 0000,
     * and hence we did not observe any issue.
     * If EVE is disabled, then also DO NOT remove this EVE1_VECS section @0x80000000,
     * if no AppImage for EVE. This could overwrites the code/data loaded at 0x80000000
     */

    /* Changes for ECC
     * EVE code will run only from non-ECC region
     * All code section should be next to non-ECC region (using EVE section) to
     * allow them to be easily taken out of ECC region for debugging.
     * Make sure DSP1_DATA_ADDR_2 and DSP2_DATA_ADDR_2 are immediately after
     * SR1_BUFF_ECC_QM_ADDR and should be 2*MB in total - this size should
     * be kept constant across all platforms and should match the increment
     * to heapStats.heapSize in utils_xmc_mpu.c
     */
    EVE1_VECS_ADDR             = DDR3_BASE_ADDR_0;
    EVE1_CODE_ADDR             = EVE1_VECS_ADDR             + EVE1_VECS_SIZE;
    EVE1_DATA_ADDR             = EVE1_CODE_ADDR             + EVE1_CODE_SIZE;
    EVE2_VECS_ADDR             = EVE1_DATA_ADDR             + EVE1_DATA_SIZE;
    EVE2_CODE_ADDR             = EVE2_VECS_ADDR             + EVE2_VECS_SIZE;
    EVE2_DATA_ADDR             = EVE2_CODE_ADDR             + EVE2_CODE_SIZE;
    NDK_DATA_ADDR              = EVE2_DATA_ADDR             + EVE2_DATA_SIZE;
    IPU1_1_CODE_ADDR           = NDK_DATA_ADDR              + NDK_DATA_SIZE;
    IPU1_0_CODE_ADDR           = IPU1_1_CODE_ADDR           + IPU1_1_CODE_SIZE;
    IPU2_CODE_ADDR             = IPU1_0_CODE_ADDR           + IPU1_0_CODE_SIZE;
    DSP1_CODE_ADDR             = IPU2_CODE_ADDR             + IPU2_CODE_SIZE;
    DSP2_CODE_ADDR             = DSP1_CODE_ADDR             + DSP1_CODE_SIZE;
    IPU1_1_DATA_ADDR           = DSP2_CODE_ADDR             + DSP2_CODE_SIZE;
    IPU1_0_DATA_ADDR           = IPU1_1_DATA_ADDR           + IPU1_1_DATA_SIZE;
    IPU2_DATA_ADDR             = IPU1_0_DATA_ADDR           + IPU1_0_DATA_SIZE;
    DSP1_DATA_ADDR             = IPU2_DATA_ADDR             + IPU2_DATA_SIZE;
    DSP2_DATA_ADDR             = DSP1_DATA_ADDR             + DSP1_DATA_SIZE;
    A15_0_DATA_ADDR            = DSP2_DATA_ADDR             + DSP2_DATA_SIZE;
    SR1_BUFF_ECC_ASIL_ADDR     = A15_0_DATA_ADDR            + A15_0_DATA_SIZE;
    SR1_BUFF_ECC_QM_ADDR       = SR1_BUFF_ECC_ASIL_ADDR     + SR1_BUFF_ECC_ASIL_SIZE;
    DSP1_DATA_ADDR_2           = SR1_BUFF_ECC_QM_ADDR       + SR1_BUFF_ECC_QM_SIZE;
    DSP2_DATA_ADDR_2           = DSP1_DATA_ADDR_2           + DSP1_DATA_SIZE_2;
    SR1_BUFF_NON_ECC_ASIL_ADDR = DSP2_DATA_ADDR_2           + DSP2_DATA_SIZE_2;
    SR1_FRAME_BUFFER_ADDR      = SR1_BUFF_NON_ECC_ASIL_ADDR + SR1_BUFF_NON_ECC_ASIL_SIZE;

    /* Non Cached Section */
    /* The start address of the second mem section should be 16MB aligned.
     * This alignment is a must as a single 16MB mapping is used for EVE
     * to map SR0, REMOTE_LOG_MEM sections.
     * tlb_config_eveX.c need to be modified otherwise
     */
    SR0_ADDR                    = DDR3_BASE_ADDR_1;
    REMOTE_LOG_ADDR             = SR0_ADDR              + SR0_SIZE;
    LINK_STATS_ADDR             = REMOTE_LOG_ADDR       + REMOTE_LOG_SIZE;
    SYSTEM_IPC_SHM_ADDR         = LINK_STATS_ADDR       + LINK_STATS_SIZE;
    HDVPSS_DESC_ADDR            = SYSTEM_IPC_SHM_ADDR   + SYSTEM_IPC_SHM_SIZE;
    OPENVX_SHM_ADDR             = HDVPSS_DESC_ADDR      + HDVPSS_DESC_SIZE;

    if ((SR1_FRAME_BUFFER_ADDR + SR1_FRAME_BUFFER_SIZE) > (DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0))
    {
      throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
                               "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0) +
                               "\nActual End: " + "0x" + java.lang.Long.toHexString(SR1_FRAME_BUFFER_ADDR + SR1_FRAME_BUFFER_SIZE));
    }

    if(java.lang.System.getenv("OPENVX_INCLUDE")=="yes")
    {
        if ((OPENVX_SHM_ADDR + OPENVX_SHM_SIZE) > (DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1))
        {
            throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR with OpenVx",
                               "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1) +
                               "\nActual End: " + "0x" + java.lang.Long.toHexString(OPENVX_SHM_ADDR + OPENVX_SHM_SIZE));
        }
    }
    else
    {
        if ((HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE) > (DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1))
        {
            throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR",
                               "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1) +
                               "\nActual End: " + "0x" + java.lang.Long.toHexString(HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE));
        }
    }

    if ((DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) > (TOTAL_MEM_SIZE))
    {
      throw xdc.$$XDCException("MEMORY_MAP EXCEEDS DDR SIZE ERROR ",
                               "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) +
                               "\nActual End: " + "0x" + java.lang.Long.toHexString(TOTAL_MEM_SIZE));
    }

    var memory = new Array();
    var index = 0;

    memory[index++] = ["IPU1_1_CODE_MEM", {
            comment : "IPU1_1_CODE_MEM",
            name    : "IPU1_1_CODE_MEM",
            base    : IPU1_1_CODE_ADDR,
            len     : IPU1_1_CODE_SIZE
        }];
    memory[index++] = ["IPU1_1_DATA_MEM", {
            comment : "IPU1_1_DATA_MEM",
            name    : "IPU1_1_DATA_MEM",
            base    : IPU1_1_DATA_ADDR,
            len     : IPU1_1_DATA_SIZE
        }];
    memory[index++] = ["IPU1_0_CODE_MEM", {
            comment : "IPU1_0_CODE_MEM",
            name    : "IPU1_0_CODE_MEM",
            base    : IPU1_0_CODE_ADDR,
            len     : IPU1_0_CODE_SIZE
        }];
    memory[index++] = ["IPU1_0_DATA_MEM", {
            comment : "IPU1_0_DATA_MEM",
            name    : "IPU1_0_DATA_MEM",
            base    : IPU1_0_DATA_ADDR,
            len     : IPU1_0_DATA_SIZE
        }];
    memory[index++] = ["IPU2_CODE_MEM", {
            comment : "IPU2_CODE_MEM",
            name    : "IPU2_CODE_MEM",
            base    : IPU2_CODE_ADDR,
            len     : IPU2_CODE_SIZE
        }];
    memory[index++] = ["IPU2_DATA_MEM", {
            comment : "IPU2_DATA_MEM",
            name    : "IPU2_DATA_MEM",
            base    : IPU2_DATA_ADDR,
            len     : IPU2_DATA_SIZE
        }];
    memory[index++] = ["DSP1_CODE_MEM", {
            comment : "DSP1_CODE_MEM",
            name    : "DSP1_CODE_MEM",
            base    : DSP1_CODE_ADDR,
            len     : DSP1_CODE_SIZE
        }];
    memory[index++] = ["DSP1_DATA_MEM", {
            comment : "DSP1_DATA_MEM",
            name    : "DSP1_DATA_MEM",
            base    : DSP1_DATA_ADDR,
            len     : DSP1_DATA_SIZE
        }];
    memory[index++] = ["DSP1_DATA_MEM_2", {
            comment : "DSP1_DATA_MEM_2",
            name    : "DSP1_DATA_MEM_2",
            base    : DSP1_DATA_ADDR_2,
            len     : DSP1_DATA_SIZE_2
        }];

    memory[index++] = ["DSP2_CODE_MEM", {
            comment : "DSP2_CODE_MEM",
            name    : "DSP2_CODE_MEM",
            base    : DSP2_CODE_ADDR,
            len     : DSP2_CODE_SIZE
        }];
    memory[index++] = ["DSP2_DATA_MEM", {
            comment : "DSP2_DATA_MEM",
            name    : "DSP2_DATA_MEM",
            base    : DSP2_DATA_ADDR,
            len     : DSP2_DATA_SIZE
        }];
    memory[index++] = ["DSP2_DATA_MEM_2", {
            comment : "DSP2_DATA_MEM_2",
            name    : "DSP2_DATA_MEM_2",
            base    : DSP2_DATA_ADDR_2,
            len     : DSP2_DATA_SIZE_2
        }];

    memory[index++] = ["NDK_MEM", {
            comment : "NDK_MEM",
            name    : "NDK_MEM",
            base    : NDK_DATA_ADDR,
            len     : NDK_DATA_SIZE
        }];
    memory[index++] = ["A15_0_DATA_MEM", {
            comment : "A15_0_DATA_MEM",
            name    : "A15_0_DATA_MEM",
            base    : A15_0_DATA_ADDR,
            len     : A15_0_DATA_SIZE
        }];

    memory[index++] = ["EVE1_VECS_MEM", {
            comment : "EVE1_VECS_MEM",
            name    : "EVE1_VECS_MEM",
            base    : EVE1_VECS_ADDR,
            len     : EVE1_VECS_SIZE
        }];
    memory[index++] = ["EVE1_CODE_MEM", {
            comment : "EVE1_CODE_MEM",
            name    : "EVE1_CODE_MEM",
            base    : EVE1_CODE_ADDR,
            len     : EVE1_CODE_SIZE
        }];
    memory[index++] = ["EVE1_DATA_MEM", {
            comment : "EVE1_DATA_MEM",
            name    : "EVE1_DATA_MEM",
            base    : EVE1_DATA_ADDR,
            len     : EVE1_DATA_SIZE
        }];
    memory[index++] = ["EVE2_VECS_MEM", {
            comment : "EVE2_VECS_MEM",
            name    : "EVE2_VECS_MEM",
            base    : EVE2_VECS_ADDR,
            len     : EVE2_VECS_SIZE
        }];
    memory[index++] = ["EVE2_CODE_MEM", {
            comment : "EVE2_CODE_MEM",
            name    : "EVE2_CODE_MEM",
            base    : EVE2_CODE_ADDR,
            len     : EVE2_CODE_SIZE
        }];
    memory[index++] = ["EVE2_DATA_MEM", {
            comment : "EVE2_DATA_MEM",
            name    : "EVE2_DATA_MEM",
            base    : EVE2_DATA_ADDR,
            len     : EVE2_DATA_SIZE
        }];
    memory[index++] = ["SR1_FRAME_BUFFER_MEM", {
            comment : "SR1_FRAME_BUFFER_MEM",
            name    : "SR1_FRAME_BUFFER_MEM",
            base    : SR1_FRAME_BUFFER_ADDR,
            len     : SR1_FRAME_BUFFER_SIZE
        }];
    memory[index++] = ["SR1_BUFF_ECC_ASIL_MEM", {
            comment : "SR1_BUFF_ECC_ASIL_MEM",
            name    : "SR1_BUFF_ECC_ASIL_MEM",
            base    : SR1_BUFF_ECC_ASIL_ADDR,
            len     : SR1_BUFF_ECC_ASIL_SIZE
    }];
    memory[index++] = ["SR1_BUFF_ECC_QM_MEM", {
            comment : "SR1_BUFF_ECC_QM_MEM",
            name    : "SR1_BUFF_ECC_QM_MEM",
            base    : SR1_BUFF_ECC_QM_ADDR,
            len     : SR1_BUFF_ECC_QM_SIZE
    }];
    memory[index++] = ["SR1_BUFF_NON_ECC_ASIL_MEM", {
            comment : "SR1_BUFF_NON_ECC_ASIL_MEM",
            name    : "SR1_BUFF_NON_ECC_ASIL_MEM",
            base    : SR1_BUFF_NON_ECC_ASIL_ADDR,
            len     : SR1_BUFF_NON_ECC_ASIL_SIZE
    }];
    memory[index++] = ["SR0", {
            comment : "SR0",
            name    : "SR0",
            base    : SR0_ADDR,
            len     : SR0_SIZE
        }];
    memory[index++] = ["HDVPSS_DESC_MEM", {
            comment : "HDVPSS_DESC_MEM",
            name    : "HDVPSS_DESC_MEM",
            base    : HDVPSS_DESC_ADDR,
            len     : HDVPSS_DESC_SIZE
        }];
    memory[index++] = ["REMOTE_LOG_MEM", {
            comment : "REMOTE_LOG_MEM",
            name    : "REMOTE_LOG_MEM",
            base    : REMOTE_LOG_ADDR,
            len     : REMOTE_LOG_SIZE
        }];
    memory[index++] = ["LINK_STATS_MEM", {
            comment : "LINK_STATS_MEM",
            name    : "LINK_STATS_MEM",
            base    : LINK_STATS_ADDR,
            len     : LINK_STATS_SIZE
        }];
    memory[index++] = ["SYSTEM_IPC_SHM_MEM", {
            comment : "SYSTEM_IPC_SHM_MEM",
            name    : "SYSTEM_IPC_SHM_MEM",
            base    : SYSTEM_IPC_SHM_ADDR,
            len     : SYSTEM_IPC_SHM_SIZE
        }];

    xdc.print("# !!! Core is [" + core + "] !!!" );

    memory[index++] = ["DSP1_L2_SRAM", {
            comment: "DSP1_L2_SRAM",
            name: "DSP1_L2_SRAM",
            base: DSP1_L2_SRAM_ADDR,
            len:  DSP1_L2_SRAM_SIZE
        }];
    memory[index++] = ["DSP2_L2_SRAM", {
            comment: "DSP2_L2_SRAM",
            name: "DSP2_L2_SRAM",
            base: DSP2_L2_SRAM_ADDR,
            len:  DSP2_L2_SRAM_SIZE
        }];

if(java.lang.System.getenv("OPENCL_INCLUDE") == "yes")
{
/* This is a dummy section needed for OpenCL */
        L1DSRAM_ADDR = 0x00F00000;
        L1DSRAM_SIZE = 0x00008000;
        OCL_LOCAL_ADDR = 0x0083B000;
        OCL_LOCAL_SIZE = 0x00004000;
        memory[index++] = ["L1DSRAM", {
            comment: "L1DSRAM",
            name: "L1DSRAM",
            base: L1DSRAM_ADDR,
            len:  L1DSRAM_SIZE
        }];

}

    if(java.lang.System.getenv("OPENVX_INCLUDE")=="yes")
    {
        memory[index++] = ["OPENVX_SHM_MEM", {
                comment: "OPENVX_SHM_MEM",
                name: "OPENVX_SHM_MEM",
                base: OPENVX_SHM_ADDR,
               len:  OPENVX_SHM_SIZE
        }];
    }

    return (memory);
}

2. vision_sdk/links_fw/src/rtos/bios_app_common/tda2px/a15_0/a15_0.cfg

/*******************************************************************************
*  file name: a15_0.cfg
*  Set A15 core 0 specific configuration
*
*******************************************************************************/

var CurrentPlatform = java.lang.System.getenv("PLATFORM");
var DualA15_smpbios = java.lang.System.getenv("DUAL_A15_SMP_BIOS");
var OpenCL = java.lang.System.getenv("OPENCL_INCLUDE");
var OpenCV = java.lang.System.getenv("ENABLE_OPENCV");

xdc.print("# !!! Current build platform is [" + CurrentPlatform + "] !!!" );

xdc.loadPackage('ti.sysbios').profile = "release";
xdc.loadCapsule("src/rtos/bios_app_common/tda2px/cfg/BIOS_common.cfg");

/* root of the configuration object model */
var Program = xdc.useModule('xdc.cfg.Program');

xdc.useModule('ti.sysbios.gates.GateHwi');
var BIOS = xdc.useModule('ti.sysbios.BIOS');
if(OpenCL=="yes")
{
var SecondsClock = xdc.useModule('ti.sysbios.hal.SecondsClock');
}

BIOS.cpuFreq.hi = 0;
BIOS.cpuFreq.lo = 750000000; /* 750 MHz */

if(DualA15_smpbios=="yes")
{
   BIOS.smpEnabled = true;
}
else
{
   BIOS.smpEnabled = false;
}

/*
 *  ======== IPC Configuration ========
 */
Program.global.procName = "HOST";
xdc.loadCapsule("src/rtos/bios_app_common/tda2px/cfg/IPC_common.cfg");

var NdkProcToUse = java.lang.System.getenv("NDK_PROC_TO_USE");

if(NdkProcToUse=="a15_0")
{
   xdc.print("# !!! Linking to NDK !!!" );
   xdc.loadCapsule("src/rtos/bios_app_common/tda2px/cfg/NDK_config.cfg");
}

/*
 *  ======== Operating System Configuration ========
 */

/* no rts heap */
Program.heap = 0;
Program.argSize = 100;  /* minimum size */
if(OpenCL=="yes")
{
    Program.stack = 0x4000;
}
else
{
    Program.stack = 0x4000;
}

/* create a default heap */
var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
var heapMemParams = new HeapMem.Params();
if(OpenCL=="yes")
{
    heapMemParams.size = 0x6000000;
}
else
{
    heapMemParams.size = 0x600000;
}

var Memory = xdc.useModule('xdc.runtime.Memory');
Memory.defaultHeapInstance = HeapMem.create(heapMemParams);
if(OpenCL=="yes")
{
    Memory.defaultHeapSize = 0x6000000;
}

/* Enable Cache */
if(DualA15_smpbios=="yes")
{
   var Cache = xdc.useModule('ti.sysbios.family.arm.a15.smp.Cache');
}
else
{
   var Cache = xdc.useModule('ti.sysbios.family.arm.a15.Cache');
}
Cache.enableCache = true;

/***********************************************
 *              MMU Configuration              *
 ***********************************************/
var Mmu = xdc.useModule('ti.sysbios.family.arm.a15.Mmu');
Mmu.enableMMU = true;

/******************************************************************************
 *
 * SYS/BIOS assigns the following defaults to MAIR0 ATTR0, ATTR1 and ATTR2:
 *
 * ATTR0 -> 0x44 (mark memory region as non-cacheable normal memory)
 * ATTR1 -> 0x00 (mark memory region as device memory, i.e. strongly
 * ordered and non-cacheable)
 * ATTR2 -> 0xFF (mark memory region as normal memory, RW cacheable and
 * RW allocate)
 ******************************************************************************
 */

// descriptor attribute structure
var attrs0 = new Mmu.DescriptorAttrs();

Mmu.initDescAttrsMeta(attrs0);

attrs0.type = Mmu.DescriptorType_BLOCK;    // BLOCK descriptor
attrs0.noExecute = true;                   // not executable
attrs0.accPerm = 0;                        // read/write at PL1
attrs0.shareable = 2;                      // shareable
attrs0.attrIndx = 1;                       // strongly ordered and non-cacheable

// Set the descriptor for each entry in the address range
// NOTE: Currently mapping all region as non-cacheable, device memory.
//If in future application want to use OCMC memories it needs to remove corresponding MMU entries from below and make it cacheable.
for (var i=0x40000000; i < 0x60000000; i = i + 0x00200000) {
    // Each 'BLOCK' descriptor entry spans a 2MB address range
    Mmu.setSecondLevelDescMeta(i, i, attrs0);
}

// descriptor attribute structure
var attrs1 = new Mmu.DescriptorAttrs();

Mmu.initDescAttrsMeta(attrs1);
attrs1.type = Mmu.DescriptorType_BLOCK;    // BLOCK descriptor
attrs1.shareable = 2;                      // sharerable
attrs1.attrIndx = 2;                       // Cached, normal memory

// Set the descriptor for each entry in the address range
for (var i=0x80000000; i < 0xC0000000; i = i + 0x00200000) {
    // Each 'BLOCK' descriptor entry spans a 2MB address range
    Mmu.setSecondLevelDescMeta(i, i, attrs1);
}

// descriptor attribute structure
var attrs2 = new Mmu.DescriptorAttrs();

Mmu.initDescAttrsMeta(attrs2);
attrs2.type = Mmu.DescriptorType_BLOCK;    // BLOCK descriptor
attrs2.shareable = 2;                      // sharerable
attrs2.attrIndx = 0;                       // Non-cache, normal memory

// Set the descriptor for each entry in the address range
for (var i=0xA0000000; i <= 0xFFFFFFFF; i = i + 0x00200000) {
    // Each 'BLOCK' descriptor entry spans a 2MB address range
    Mmu.setSecondLevelDescMeta(i, i, attrs2);
}

// Region for NDK packet data buffers.
for (var i = 0; i < Program.cpu.memoryMap.length; i++)
{
    memSegment = Program.cpu.memoryMap[i];
    if (memSegment.name == "NDK_MEM")
    {
        var attrs3 = new Mmu.DescriptorAttrs();
        Mmu.initDescAttrsMeta(attrs3);
        attrs3.type = Mmu.DescriptorType_BLOCK;    // BLOCK descriptor
        attrs3.noExecute = true;                   // not executable
        attrs3.shareable = 2;                      // shareable
        attrs3.accPerm = 0;                        // read/write at PL1
        attrs3.attrIndx = 2;                       // Mark mem regions as cached, normal memory

        // Set the descriptor for each entry in the address range
        for (var j=memSegment.base; j < (memSegment.base + memSegment.len); j = j + 0x00200000)
        {
            // Each 'BLOCK' descriptor entry spans a 2MB address range
            Mmu.setSecondLevelDescMeta(j, j, attrs3);
        }
    }
}

/* .text is allocated as per "codeMemory" defined in .bld file.
 * .data, .stack, .bss, .sysmem, etc are allocated as per
 * "dataMemory" defined in .bld file */
Program.sectMap[".bss:extMemNonCache:remoteLogCoreShm"] = "REMOTE_LOG_MEM";
Program.sectMap[".bss:extMemNonCache:hcfResourceTable"] = "REMOTE_LOG_MEM";
Program.sectMap[".bss:extMemNonCache:ipcShm"]           = "SYSTEM_IPC_SHM_MEM";
Program.sectMap[".bss:extMemNonCache:linkStats"]        = "LINK_STATS_MEM";
if (java.lang.System.getenv("OPENVX_INCLUDE") == "yes")
{
    Program.sectMap[".bss:extMemNonCache:tiovxObjDescShm"] = "OPENVX_SHM_MEM";
}

Program.sectMap[".bss:NDK_PACKETMEM"]                   = "NDK_MEM";
Program.sectMap[".bss:NDK_MMBUFFER"]                    = "NDK_MEM";

var InitXbar    = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");

/* Exception hook function */
var ExceptionA15 = xdc.useModule('ti.sysbios.family.arm.exc.Exception');

/* enable print of exception handing info */
ExceptionA15.excHookFunc ='&Utils_a15ExceptionHookFxn';
ExceptionA15.enableDecode=true;

/* XDC runtime function */
var Error = xdc.useModule("xdc.runtime.Error");
Error.raiseHook = "&Utils_commonErrorRaiseHook";

/* Add an idle thread 'Utils_idleFxn' that monitors interrupts. */
var Idle = xdc.useModule("ti.sysbios.knl.Idle");

if (DualA15_smpbios == "yes")
{
    Idle.addCoreFunc('&Utils_idleFxn', 0);
    Idle.addCoreFunc('&Utils_idleFxn', 1);
}
else
{
    Idle.addFunc('&Utils_idleFxn');
}

/* Assign GPTimer2 to be used for BIOS Clock 1-ms tick */
/***********************************************
 *          CLOCK Module Configuraion          *
 ***********************************************/
var Clock = xdc.useModule("ti.sysbios.knl.Clock");

if(OpenCL=="yes")
{
    Clock.tickMode = Clock.TickMode_PERIODIC;
}
else
{
    Clock.tickMode = Clock.TickMode_PERIODIC;
    Clock.tickSource = Clock.TickSource_USER;
}

/***********************************************
*           Timer Module Configuraion         *
***********************************************/
/* Assign GPTimer2 to be used for Timestamp */
/* Set to 1-ms Tick and Enable Wakeup for OVF interrupt */
var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
var timerParams = new Timer.Params();
timerParams.period = 1000;
timerParams.twer.ovf_wup_ena = 1;
timerParams.tiocpCfg.emufree = 1;
timerParams.tsicr.posted = 0;
/* Timer ID = 1 for GPTimer2 and input clock runs at 20 MHz */
Timer.intFreqs[1].hi = 0;
Timer.intFreqs[1].lo = 20000000;
Timer.create(1, '&mainA15TimerTick', timerParams);

/* Assign GPTimer3 to be used for Timestamp */
/* Timer ID = 2 for GPTimer3 and input clock runs at 20 MHz */
var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
var timerParams2 = new DMTimer.Params();
timerParams2.tsicr.posted = 0;
DMTimer.intFreqs[2].hi = 0;
DMTimer.intFreqs[2].lo = 20000000;
var DMTimestampProvider = xdc.useModule("ti.sysbios.timers.dmtimer.TimestampProvider");
DMTimestampProvider.timerId = 2;
DMTimestampProvider.useClockTimer = false;
var Timestamp = xdc.useModule("xdc.runtime.Timestamp");
Timestamp.SupportProxy = DMTimestampProvider;

/* Indicate GPT2 & GPT3 are used */
var TimerSupport = xdc.useModule('ti.sysbios.family.shared.vayu.TimerSupport');
TimerSupport.availMask = 0x0006;

/* In order to check how much percentange of Idle time the CPU is in Low power */
var LocalTimestampProvider = xdc.useModule('ti.sysbios.family.arm.a15.TimestampProvider');

/* Add POSIX Support */
if(OpenCV=="yes")
{
    var Settings = xdc.useModule('ti.sysbios.posix.Settings');
    Settings.supportsMutexPriority = true;
}

if(OpenCL=="yes")
{
    var Settings = xdc.useModule('ti.sysbios.posix.Settings');
    Settings.supportsMutexPriority = true;
    xdc.global.oclProcName = "HOST";
    var OCL = xdc.useModule('ti.opencl.OpenCL');
    OCL.computeUnitList = "0";
    OCL.OCL_ipc_customized = true;
    OCL.OCL_memory_customized =true;
    OCL.OCL_HOSTPROG_base = Program.cpu.memoryMap["A15_0_DATA_MEM"].base;
    OCL.OCL_HOSTPROG_len  = Program.cpu.memoryMap["SR1_FRAME_BUFFER_MEM"].base - Program.cpu.memoryMap["A15_0_DATA_MEM"].base
                            + Program.cpu.memoryMap["SR1_FRAME_BUFFER_MEM"].len;
    OCL.OCL_GLOBAL_base   = Program.cpu.memoryMap["EVE2_CODE_MEM"].base;
    OCL.OCL_GLOBAL_len    = Program.cpu.memoryMap["EVE2_CODE_MEM"].len;
    OCL.OCL_LOCAL_base    = Program.cpu.memoryMap["OCMC_RAM2"].base;
    OCL.OCL_LOCAL_len     = Program.cpu.memoryMap["OCMC_RAM2"].len;
}

3. vision_sdk/links_fw/src/rtos/bios_app_common/tda2px/ipu1_0/Ipu1_0.cfg

/*******************************************************************************
*  file name: Ipu1_0.cfg
*  Set IPU1 core0 specific configuration
*  Platform: VAYU_bios_elf
*  Target: ti.targets.arm.elf.M4
*
*******************************************************************************/

var CurrentPlatform = java.lang.System.getenv("PLATFORM");
var A15TargetOS     = java.lang.System.getenv("A15_TARGET_OS");
if (A15TargetOS == "Qnx")
{
    A15TargetOS = "Linux";
}

xdc.print("# !!! Current build platform is [" + CurrentPlatform + "] !!!" );

xdc.loadPackage('ti.sysbios').profile = "release";
xdc.loadCapsule("src/rtos/bios_app_common/tda2px/cfg/BIOS_common.cfg");

var NdkProcToUse = java.lang.System.getenv("NDK_PROC_TO_USE");

if(NdkProcToUse=="ipu1_0")
{
    xdc.print("# !!! Linking to NDK !!!" );
    xdc.loadCapsule("src/rtos/bios_app_common/tda2px/cfg/NDK_config.cfg");
}

var Timer       = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
/* root of the configuration object model */
var Program      = xdc.useModule('xdc.cfg.Program');
var GIO          = xdc.useModule('ti.sysbios.io.GIO');

var Core         = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
/* set the ipuId and coreId */
Core.ipuId = 1;
Core.id = 0;

var BIOS = xdc.useModule('ti.sysbios.BIOS');
if (A15TargetOS == "Linux")
{
BIOS.smpEnabled = true;
}
else
{
BIOS.smpEnabled = false;
}

/* Physical address of VPDMA desc is HDVPSS_DESC_ADDR */
Program.global.XDC_CFG_VPDMA_DESC_PHYS_ADDR  = Program.cpu.memoryMap['HDVPSS_DESC_MEM'].base;

/* Memory section address and size */
Program.global.XDC_SR1_FRAME_BUFFER_ADDR = Program.cpu.memoryMap['SR1_FRAME_BUFFER_MEM'].base;
Program.global.XDC_SR1_FRAME_BUFFER_SIZE = Program.cpu.memoryMap['SR1_FRAME_BUFFER_MEM'].len;
Program.global.XDC_SR1_BUFF_ECC_ASIL_ADDR = Program.cpu.memoryMap['SR1_BUFF_ECC_ASIL_MEM'].base;
Program.global.XDC_SR1_BUFF_ECC_ASIL_SIZE = Program.cpu.memoryMap['SR1_BUFF_ECC_ASIL_MEM'].len;
Program.global.XDC_SR1_BUFF_ECC_QM_ADDR = Program.cpu.memoryMap['SR1_BUFF_ECC_QM_MEM'].base;
Program.global.XDC_SR1_BUFF_ECC_QM_SIZE = Program.cpu.memoryMap['SR1_BUFF_ECC_QM_MEM'].len;
Program.global.XDC_SR1_BUFF_NON_ECC_ASIL_ADDR = Program.cpu.memoryMap['SR1_BUFF_NON_ECC_ASIL_MEM'].base;
Program.global.XDC_SR1_BUFF_NON_ECC_ASIL_SIZE = Program.cpu.memoryMap['SR1_BUFF_NON_ECC_ASIL_MEM'].len;

/*
 *  ======== IPU1 CORE0 Processor (primary core) ========
 *  AMMU config need to be done only on one core
 *  This is done in primary core (CORE0) , so do it here
 */
/***********************************************
 *              Ammu Configuraiton             *
 ***********************************************/
if (A15TargetOS == "Linux")
{
    var ammu = xdc.loadCapsule("Ammu1_linux.cfg");
}
if (A15TargetOS == "Bios")
{
    var ammu = xdc.loadCapsule("Ammu1_bios.cfg");
}
ammu.init();

/*
 *  ======== IPC Configuration ========
 */
Program.global.procName = "IPU1-0";
xdc.loadCapsule("src/rtos/bios_app_common/tda2px/cfg/IPC_common.cfg");

/*
 *  ======== Operating System Configuration ========
 */

/* no rts heap */
Program.heap = 0;
Program.argSize = 100;  /* minimum size */
Program.stack = 0x4000;

/* create a default heap */
var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
var heapMemParams = new HeapMem.Params();
heapMemParams.size = 0x40000;

var Memory = xdc.useModule('xdc.runtime.Memory');
Memory.defaultHeapInstance = HeapMem.create(heapMemParams);
Memory.defaultHeapSize  = 0x15000;

Program.sectMap[".bss:extMemNonCache:remoteLogCoreShm"] = "REMOTE_LOG_MEM";
Program.sectMap[".bss:extMemNonCache:hcfResourceTable"] = "REMOTE_LOG_MEM";
Program.sectMap[".bss:extMemNonCache:ipcShm"] = "SYSTEM_IPC_SHM_MEM";
Program.sectMap[".bss:extMemNonCache:linkStats"] = "LINK_STATS_MEM";
if (java.lang.System.getenv("OPENVX_INCLUDE") == "yes")
{
    Program.sectMap[".bss:extMemNonCache:tiovxObjDescShm"] = "OPENVX_SHM_MEM";
}

Program.sectMap[".text"]                      = "IPU1_0_CODE_MEM";
Program.sectMap[".const"]                     = "IPU1_0_CODE_MEM";
Program.sectMap[".plt"]                       = "IPU1_0_CODE_MEM";

Program.sectMap[".data"]                      = "IPU1_0_DATA_MEM";
Program.sectMap[".bss"]                       = "IPU1_0_DATA_MEM";
Program.sectMap[".neardata"]                  = "IPU1_0_DATA_MEM";
Program.sectMap[".rodata"]                    = "IPU1_0_DATA_MEM";

Program.sectMap[".bss:taskStackSection"]      = "IPU1_0_DATA_MEM";

var ipu_pri     = java.lang.System.getenv("IPU_PRIMARY_CORE");
if (ipu_pri == "ipu1_0")
{
Program.sectMap[".bss:extMemNonCache:vpdma"]  = "HDVPSS_DESC_MEM";
Program.sectMap[".bss:heapMemDDR"]            = "SR1_FRAME_BUFFER_MEM";
Program.sectMap[".bss:heapMemDDREccAsil"]     = "SR1_BUFF_ECC_ASIL_MEM";
Program.sectMap[".bss:heapMemDDREccQM"]       = "SR1_BUFF_ECC_QM_MEM";
Program.sectMap[".bss:heapMemDDRNonEccAsil"]  = "SR1_BUFF_NON_ECC_ASIL_MEM";
Program.sectMap[".bss:heapMemOCMC"]           = "OCMC_RAM1";

Program.sectMap[".bss:NDK_PACKETMEM"]         = "NDK_MEM";
Program.sectMap[".bss:NDK_MMBUFFER"]          = "NDK_MEM";

var DSP1_DATA_MEM = Program.cpu.memoryMap['DSP1_DATA_MEM'];
Program.global.gXdcDsp1DataAddr = DSP1_DATA_MEM.base;
Program.global.gXdcDsp1DataSize = DSP1_DATA_MEM.len;
var DSP2_DATA_MEM = Program.cpu.memoryMap['DSP2_DATA_MEM'];
Program.global.gXdcDsp2DataAddr = DSP2_DATA_MEM.base;
Program.global.gXdcDsp2DataSize = DSP2_DATA_MEM.len;
var EVE1_DATA_MEM = Program.cpu.memoryMap['EVE1_DATA_MEM'];
Program.global.gXdcEve1DataAddr = EVE1_DATA_MEM.base;
Program.global.gXdcEve1DataSize = EVE1_DATA_MEM.len;

/* The following value is used by L3FW, so subtract 0x20000000 to get
 * physical address. M4 uses the alias at 0xA0000000.
 */
var LINK_STATS_MEM = Program.cpu.memoryMap['LINK_STATS_MEM'];
Program.global.gXdcLinkStatsAddr = LINK_STATS_MEM.base - 0x20000000;
Program.global.gXdcLinkStatsSize = LINK_STATS_MEM.len;

if(java.lang.System.getenv("IVAHD_INCLUDE")=="yes")
{
    xdc.loadCapsule("src/rtos/bios_app_common/tda2px/cfg/RMAN_IRES_iva.cfg");
}
}

/* Exception hook function */
var HwiM3       = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');

/* enable print of exception handing info */
HwiM3.enableException = true;
HwiM3.nvicCCR.DIV_0_TRP = 1;
HwiM3.excHookFunc = '&Utils_m4ExceptionHookFxn';

/* XDC runtime function */
var Error = xdc.useModule("xdc.runtime.Error");
Error.raiseHook = "&Utils_commonErrorRaiseHook";

var InitXbar    = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");

    /* Add an idle thread 'Utils_idleFxn' that monitors interrupts. */
    var Idle = xdc.useModule("ti.sysbios.knl.Idle");
    Idle.addFunc('&Utils_idleFxn');

if (A15TargetOS == "Linux")
{
    xdc.loadCapsule("src/rtos/bios_app_common/tda2px/ipu1_0/Ipu1_0_a15_linux.cfg");
}
else
{
    /***********************************************
     *          CLOCK Module Configuraion          *
     ***********************************************/
    var Clock = xdc.useModule("ti.sysbios.knl.Clock");
    Clock.tickMode = Clock.TickMode_PERIODIC;
    Clock.tickSource = Clock.TickSource_USER;

    /***********************************************
    *           Timer Module Configuraion         *
    ***********************************************/
    var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');

    Timer.intFreqs[8].hi = 0;
    /* system clock runs at 20 MHz */
    Timer.intFreqs[8].lo = 20000000;

    var timerParams = new Timer.Params();
    timerParams.period = 1000;
    timerParams.twer.ovf_wup_ena = 1;
    timerParams.tiocpCfg.emufree = 1;
    timerParams.tsicr.posted = 0;

    Timer.create(8, '&mainIPU1_C0TimerTick', timerParams);

    var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
    var timerParams2 = new DMTimer.Params();
    timerParams2.tsicr.posted = 0;

    DMTimer.intFreqs[10].hi = 0;
    DMTimer.intFreqs[10].lo = 20000000;
    var DMTimestampProvider = xdc.useModule("ti.sysbios.timers.dmtimer.TimestampProvider");
    DMTimestampProvider.timerId = 10;
    DMTimestampProvider.useClockTimer = false;
    var Timestamp = xdc.useModule("xdc.runtime.Timestamp");
    Timestamp.SupportProxy = DMTimestampProvider;

    /* allocate timer 9 to IPU0 */
    var TimerSupport = xdc.useModule('ti.sysbios.family.shared.vayu.TimerSupport');
    TimerSupport.availMask = 0x0500;

    if (java.lang.System.getenv("ENABLE_TASK_PROFILE_UTIL") == "yes")
    {
        /***********************************************
         * Task Timer utility *
         ***********************************************/
        var Task = xdc.useModule('ti.sysbios.knl.Task');
        /* Define and add one Task Hook Set */
        Task.addHookSet({
            registerFxn: '&Utils_taskTimerRegisterHook',
            createFxn: '&Utils_taskTimerCreateHook',
            readyFxn: '&Utils_taskTimerReadyHook',
            switchFxn: '&Utils_taskTimerSwitchHook',
            exitFxn: '&Utils_taskTimerExitHook',
            deleteFxn: '&Utils_taskTimerDeleteHook',
            });
    }

}

/* In order to check how much percentange of Idle time the CPU is in Low power */
var LocalTimestampProvider = xdc.useModule('ti.sysbios.family.arm.ducati.TimestampProvider');

4. vision_sdk/links_fw/src/rtos/bios_app_common/tda2px/ipu1_0/Ammu1_bios.cfg

/*******************************************************************************
*  file name: Ammu1.cfg
*  Set IPU1 (core 0 and core 1) AMMU configuration
*
*******************************************************************************/

/******************************************************************************
 *
 * NOTE:
 *
 * Region 0x42000000 to 0x44000000 (32MB) is BitBand region in IPU.
 *
 * Any L3/L4 peripherals mapped to this region must be accsssed via virtual
 * address on IPU side.
 *
 * On TDA2xx below peripherals fall in this BitBand region
 *   - EVE1/2/3/4 MBOX0/1
 *   - System EDMA
 *
 * Further IPC package by default acceses System mailbox's on IPU side via
 * virtual address's
 *
 * In AMMU config, one large page can be used to do this virutal to physical
 * address mapping as shown below,
 *
 *   Virutal Address          Physical Address
 *  0x60000000:0x7FFFFFFF -> 0x40000000:0x5FFFFFFF   (512MB)
 *
 * However this wastes a large page which can be used for other purposes
 * Ex, mapping GPMC NOR memory of 64MB.
 *
 * Hence AMMU config below maps multiple small and medium pages to specific
 * address ranges of the required peripherals.
 *
 ******************************************************************************
 */

function init()
{
    var Program = xdc.useModule('xdc.cfg.Program');
    var Cache = xdc.useModule('ti.sysbios.hal.unicache.Cache');
    Cache.enableCache = true;

    var AMMU = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
    AMMU.configureAmmu = true;

    /*********************** Medium Pages *************************/

    /* ISS */
    var entry = AMMU.mediumPages[0];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x62200000;
    entry.translatedAddress = 0x42200000;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.size = AMMU.Medium_256K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
    entry.L1_allocate    = AMMU.AllocatePolicy_NON_ALLOCATE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /* ISS */
    var entry = AMMU.mediumPages[1];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x62240000;
    entry.translatedAddress = 0x42240000;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.size = AMMU.Medium_256K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
    entry.L1_allocate    = AMMU.AllocatePolicy_NON_ALLOCATE;
    entry.L1_posted = AMMU.PostedPolicy_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /*********************** Small Pages *************************/

    /* EVE1 MBOX0 */
    var entry = AMMU.smallPages[2];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x62088000;
    entry.translatedAddress = 0x42088000;
    entry.size = AMMU.Small_16K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /* EVE1 MBOX1 */
    var entry = AMMU.smallPages[3];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x6208C000;
    entry.translatedAddress = 0x4208C000;
    entry.size = AMMU.Small_16K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /* EVE2 MBOX0 */
    var entry = AMMU.smallPages[4];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x62188000;
    entry.translatedAddress = 0x42188000;
    entry.size = AMMU.Small_16K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /* EVE2 MBOX1 */
    var entry = AMMU.smallPages[5];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x6218C000;
    entry.translatedAddress = 0x4218C000;
    entry.size = AMMU.Small_16K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /* System EDMA TPCC */
    var entry = AMMU.smallPages[6];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x63300000;
    entry.translatedAddress = 0x43300000;
    entry.size = AMMU.Small_16K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /* System EDMA TPCC */
    var entry = AMMU.smallPages[7];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x63304000;
    entry.translatedAddress = 0x43304000;
    entry.size = AMMU.Small_16K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /* System Mailbox 5, 6 */
    var entry = AMMU.smallPages[8];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x68840000;
    entry.translatedAddress = 0x48840000;
    entry.size = AMMU.Small_16K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;
   
    /* System Mailbox 7, 8 */
    var entry = AMMU.smallPages[9];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x68844000;
    entry.translatedAddress = 0x48844000;
    entry.size = AMMU.Small_16K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /*********************** Large Pages *************************/
    var entry = AMMU.largePages[0];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x40000000;
    entry.translatedAddress = 0x40000000;
    entry.size = AMMU.Large_512M;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /* map program code/data memory into ammu (cacheable) */
    var entry = AMMU.largePages[1];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x80000000;
    entry.translatedAddress = 0x80000000;
    entry.size = AMMU.Large_512M;
    entry.L1_cacheable = AMMU.CachePolicy_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_POSTED;
    entry.L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
    entry.L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /* map SR_0 data memory into ammu (non-cacheable) */
    var entry = AMMU.largePages[2];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0xA0000000;
    entry.translatedAddress = 0xA0000000;
    entry.size = AMMU.Large_512M;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    var entry = AMMU.largePages[3];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x60000000;
    entry.translatedAddress = 0x40000000;
    entry.size = AMMU.Large_512M;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

}

5. vision_sdk/links_fw/src/rtos/bios_app_common/tda2px/ipu2/Ipu2.cfg

/*******************************************************************************
*  file name: Ipu2.cfg
*  Set IPU2 core0 & core1 specific configuration
*  Platform: VAYU_bios_elf
*  Target: ti.targets.arm.elf.M4
*
*******************************************************************************/

var CurrentPlatform = java.lang.System.getenv("PLATFORM");
var A15TargetOS     = java.lang.System.getenv("A15_TARGET_OS");
if (A15TargetOS == "Qnx")
{
    A15TargetOS = "Linux";
}

xdc.print("# !!! Current build platform is [" + CurrentPlatform + "] !!!" );

xdc.loadPackage('ti.sysbios').profile = "release";
xdc.loadCapsule("src/rtos/bios_app_common/tda2px/cfg/BIOS_common.cfg");

var NdkProcToUse = java.lang.System.getenv("NDK_PROC_TO_USE");

if(NdkProcToUse=="ipu2")
{
    xdc.print("# !!! Linking to NDK !!!" );
    xdc.loadCapsule("src/rtos/bios_app_common/tda2px/cfg/NDK_config.cfg");
}

var Timer       = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
/* root of the configuration object model */
var Program      = xdc.useModule('xdc.cfg.Program');
var GIO          = xdc.useModule('ti.sysbios.io.GIO');

var Core         = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
/* set the ipuId and coreId */
Core.ipuId = 2;
Core.id = 0;

var BIOS = xdc.useModule('ti.sysbios.BIOS');
BIOS.smpEnabled = true;

/* Physical address of VPDMA desc is HDVPSS_DESC_ADDR */
Program.global.XDC_CFG_VPDMA_DESC_PHYS_ADDR  = Program.cpu.memoryMap['HDVPSS_DESC_MEM'].base;

/* Memory section address and size */
Program.global.XDC_SR1_FRAME_BUFFER_ADDR = Program.cpu.memoryMap['SR1_FRAME_BUFFER_MEM'].base;
Program.global.XDC_SR1_FRAME_BUFFER_SIZE = Program.cpu.memoryMap['SR1_FRAME_BUFFER_MEM'].len;
Program.global.XDC_SR1_BUFF_ECC_ASIL_ADDR = Program.cpu.memoryMap['SR1_BUFF_ECC_ASIL_MEM'].base;
Program.global.XDC_SR1_BUFF_ECC_ASIL_SIZE = Program.cpu.memoryMap['SR1_BUFF_ECC_ASIL_MEM'].len;
Program.global.XDC_SR1_BUFF_ECC_QM_ADDR = Program.cpu.memoryMap['SR1_BUFF_ECC_QM_MEM'].base;
Program.global.XDC_SR1_BUFF_ECC_QM_SIZE = Program.cpu.memoryMap['SR1_BUFF_ECC_QM_MEM'].len;
Program.global.XDC_SR1_BUFF_NON_ECC_ASIL_ADDR = Program.cpu.memoryMap['SR1_BUFF_NON_ECC_ASIL_MEM'].base;
Program.global.XDC_SR1_BUFF_NON_ECC_ASIL_SIZE = Program.cpu.memoryMap['SR1_BUFF_NON_ECC_ASIL_MEM'].len;

/*
 *  ======== IPU2 CORE0 Processor (primary core) ========
 *  AMMU config need to be done only on one core
 *  This is done in primary core (CORE0) , so do it here
 */
/***********************************************
 *              Ammu Configuraiton             *
 ***********************************************/
if (A15TargetOS == "Linux")
{
    var ammu = xdc.loadCapsule("Ammu2_linux.cfg");
}
if (A15TargetOS == "Bios")
{
    var ammu = xdc.loadCapsule("Ammu2_bios.cfg");
}
ammu.init();

/*
 *  ======== IPC Configuration ========
 */
Program.global.procName = "IPU2";
xdc.loadCapsule("src/rtos/bios_app_common/tda2px/cfg/IPC_common.cfg");

/*
 *  ======== Operating System Configuration ========
 */

/* no rts heap */
Program.heap = 0;
Program.argSize = 100;  /* minimum size */
Program.stack = 0x4000;

/* create a default heap */
var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
var heapMemParams = new HeapMem.Params();
heapMemParams.size = 0x40000;

var Memory = xdc.useModule('xdc.runtime.Memory');
Memory.defaultHeapInstance = HeapMem.create(heapMemParams);
Memory.defaultHeapSize  = 0x15000;

Program.sectMap[".bss:extMemNonCache:remoteLogCoreShm"] = "REMOTE_LOG_MEM";
Program.sectMap[".bss:extMemNonCache:hcfResourceTable"] = "REMOTE_LOG_MEM";
Program.sectMap[".bss:extMemNonCache:ipcShm"] = "SYSTEM_IPC_SHM_MEM";
Program.sectMap[".bss:extMemNonCache:linkStats"] = "LINK_STATS_MEM";
if (java.lang.System.getenv("OPENVX_INCLUDE") == "yes")
{
    Program.sectMap[".bss:extMemNonCache:tiovxObjDescShm"] = "OPENVX_SHM_MEM";
}

Program.sectMap[".text"]                      = "IPU2_CODE_MEM";
Program.sectMap[".const"]                     = "IPU2_CODE_MEM";
Program.sectMap[".plt"]                       = "IPU2_CODE_MEM";

Program.sectMap[".data"]                      = "IPU2_DATA_MEM";
Program.sectMap[".bss"]                       = "IPU2_DATA_MEM";
Program.sectMap[".neardata"]                  = "IPU2_DATA_MEM";
Program.sectMap[".rodata"]                    = "IPU2_DATA_MEM";

Program.sectMap[".bss:taskStackSection"]      = "IPU2_DATA_MEM";

var ipu_pri     = java.lang.System.getenv("IPU_PRIMARY_CORE");
if (ipu_pri == "ipu2")
{
Program.sectMap[".bss:extMemNonCache:vpdma"]  = "HDVPSS_DESC_MEM";
Program.sectMap[".bss:heapMemDDR"]            = "SR1_FRAME_BUFFER_MEM";
Program.sectMap[".bss:heapMemDDREccAsil"]     = "SR1_BUFF_ECC_ASIL_MEM";
Program.sectMap[".bss:heapMemDDREccQM"]       = "SR1_BUFF_ECC_QM_MEM";
Program.sectMap[".bss:heapMemDDRNonEccAsil"]  = "SR1_BUFF_NON_ECC_ASIL_MEM";
Program.sectMap[".bss:heapMemOCMC"]           = "OCMC_RAM1";

Program.sectMap[".bss:NDK_PACKETMEM"]         = "NDK_MEM";
Program.sectMap[".bss:NDK_MMBUFFER"]          = "NDK_MEM";

var DSP1_DATA_MEM = Program.cpu.memoryMap['DSP1_DATA_MEM'];
Program.global.gXdcDsp1DataAddr = DSP1_DATA_MEM.base;
Program.global.gXdcDsp1DataSize = DSP1_DATA_MEM.len;
var DSP2_DATA_MEM = Program.cpu.memoryMap['DSP2_DATA_MEM'];
Program.global.gXdcDsp2DataAddr = DSP2_DATA_MEM.base;
Program.global.gXdcDsp2DataSize = DSP2_DATA_MEM.len;
var EVE1_DATA_MEM = Program.cpu.memoryMap['EVE1_DATA_MEM'];
Program.global.gXdcEve1DataAddr = EVE1_DATA_MEM.base;
Program.global.gXdcEve1DataSize = EVE1_DATA_MEM.len;

/* The following value is used by L3FW, so subtract 0x20000000 to get
 * physical address. M4 uses the alias at 0xA0000000.
 */
var LINK_STATS_MEM = Program.cpu.memoryMap['LINK_STATS_MEM'];
Program.global.gXdcLinkStatsAddr = LINK_STATS_MEM.base - 0x20000000;
Program.global.gXdcLinkStatsSize = LINK_STATS_MEM.len;

if(java.lang.System.getenv("IVAHD_INCLUDE")=="yes")
{
    xdc.loadCapsule("src/rtos/bios_app_common/tda2px/cfg/RMAN_IRES_iva.cfg");
}
}

/* Exception hook function */
var HwiM3       = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');

/* enable print of exception handing info */
HwiM3.enableException = true;
HwiM3.nvicCCR.DIV_0_TRP = 1;
HwiM3.excHookFunc = '&Utils_m4ExceptionHookFxn';

/* XDC runtime function */
var Error = xdc.useModule("xdc.runtime.Error");
Error.raiseHook = "&Utils_commonErrorRaiseHook";

var InitXbar    = xdc.useModule("ti.sysbios.family.shared.vayu.IntXbar");

    /* Add an idle thread 'Utils_idleFxn' that monitors interrupts. */
    var Idle = xdc.useModule("ti.sysbios.knl.Idle");
    Idle.addCoreFunc('&Utils_idleFxn', 0);
    Idle.addCoreFunc('&Utils_idleFxn', 1);

if (A15TargetOS == "Linux")
{
    xdc.loadCapsule("src/rtos/bios_app_common/tda2px/ipu2/Ipu2_a15_linux.cfg");
}
else
{
    /***********************************************
     *          CLOCK Module Configuraion          *
     ***********************************************/
    var Clock = xdc.useModule("ti.sysbios.knl.Clock");
    Clock.tickMode = Clock.TickMode_PERIODIC;
    Clock.tickSource = Clock.TickSource_USER;

    /***********************************************
    *           Timer Module Configuraion         *
    ***********************************************/
    var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');

    Timer.intFreqs[8].hi = 0;
    /* system clock runs at 20 MHz */
    Timer.intFreqs[8].lo = 20000000;

    var timerParams = new Timer.Params();
    timerParams.period = 1000;
    timerParams.twer.ovf_wup_ena = 1;
    timerParams.tiocpCfg.emufree = 1;
    timerParams.tsicr.posted = 0;
    Timer.create(8, '&mainIPU2_TimerTick', timerParams);

    var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
    var timerParams2 = new DMTimer.Params();
    timerParams2.tsicr.posted = 0;
    DMTimer.intFreqs[10].hi = 0;
    DMTimer.intFreqs[10].lo = 20000000;
    var DMTimestampProvider = xdc.useModule("ti.sysbios.timers.dmtimer.TimestampProvider");
    DMTimestampProvider.timerId = 10;
    DMTimestampProvider.useClockTimer = false;
    var Timestamp = xdc.useModule("xdc.runtime.Timestamp");
    Timestamp.SupportProxy = DMTimestampProvider;

    /* allocate timer 9 to IPU0 */
    var TimerSupport = xdc.useModule('ti.sysbios.family.shared.vayu.TimerSupport');
    TimerSupport.availMask = 0x0500;
}

/* In order to check how much percentange of Idle time the CPU is in Low power */
var LocalTimestampProvider = xdc.useModule('ti.sysbios.family.arm.ducati.TimestampProvider');

6. vision_sdk/links_fw/src/rtos/bios_app_common/tda2px/ipu2/Ammu2_bios.cfg

/*******************************************************************************
*  file name: Ammu1.cfg
*  Set IPU1 (core 0 and core 1) AMMU configuration
*
*******************************************************************************/

/******************************************************************************
 *
 * NOTE:
 *
 * Region 0x42000000 to 0x44000000 (32MB) is BitBand region in IPU.
 *
 * Any L3/L4 peripherals mapped to this region must be accsssed via virtual
 * address on IPU side.
 *
 * On TDA2xx below peripherals fall in this BitBand region
 *   - EVE1/2/3/4 MBOX0/1
 *   - System EDMA
 *
 * Further IPC package by default acceses System mailbox's on IPU side via
 * virtual address's
 *
 * In AMMU config, one large page can be used to do this virutal to physical
 * address mapping as shown below,
 *
 *   Virutal Address          Physical Address
 *  0x60000000:0x7FFFFFFF -> 0x40000000:0x5FFFFFFF   (512MB)
 *
 * However this wastes a large page which can be used for other purposes
 * Ex, mapping GPMC NOR memory of 64MB.
 *
 * Hence AMMU config below maps multiple small and medium pages to specific
 * address ranges of the required peripherals.
 *
 ******************************************************************************
 */

function init()
{
    var Program = xdc.useModule('xdc.cfg.Program');
    var Cache = xdc.useModule('ti.sysbios.hal.unicache.Cache');
    Cache.enableCache = true;

    var AMMU = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
    AMMU.configureAmmu = true;

    /*********************** Medium Pages *************************/

    /* ISS */
    var entry = AMMU.mediumPages[0];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x62200000;
    entry.translatedAddress = 0x42200000;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.size = AMMU.Medium_256K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
    entry.L1_allocate    = AMMU.AllocatePolicy_NON_ALLOCATE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /* ISS */
    var entry = AMMU.mediumPages[1];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x62240000;
    entry.translatedAddress = 0x42240000;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.size = AMMU.Medium_256K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_writePolicy = AMMU.WritePolicy_WRITE_THROUGH;
    entry.L1_allocate    = AMMU.AllocatePolicy_NON_ALLOCATE;
    entry.L1_posted = AMMU.PostedPolicy_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /*********************** Small Pages *************************/

    /* EVE1 MBOX0 */
    var entry = AMMU.smallPages[2];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x62088000;
    entry.translatedAddress = 0x42088000;
    entry.size = AMMU.Small_16K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /* EVE1 MBOX1 */
    var entry = AMMU.smallPages[3];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x6208C000;
    entry.translatedAddress = 0x4208C000;
    entry.size = AMMU.Small_16K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /* EVE2 MBOX0 */
    var entry = AMMU.smallPages[4];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x62188000;
    entry.translatedAddress = 0x42188000;
    entry.size = AMMU.Small_16K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /* EVE2 MBOX1 */
    var entry = AMMU.smallPages[5];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x6218C000;
    entry.translatedAddress = 0x4218C000;
    entry.size = AMMU.Small_16K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /* System EDMA TPCC */
    var entry = AMMU.smallPages[6];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x63300000;
    entry.translatedAddress = 0x43300000;
    entry.size = AMMU.Small_16K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /* System EDMA TPCC */
    var entry = AMMU.smallPages[7];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x63304000;
    entry.translatedAddress = 0x43304000;
    entry.size = AMMU.Small_16K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /* System Mailbox 5, 6 */
    var entry = AMMU.smallPages[8];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x68840000;
    entry.translatedAddress = 0x48840000;
    entry.size = AMMU.Small_16K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;
   
    /* System Mailbox 7, 8 */
    var entry = AMMU.smallPages[9];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x68844000;
    entry.translatedAddress = 0x48844000;
    entry.size = AMMU.Small_16K;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /*********************** Large Pages *************************/
    var entry = AMMU.largePages[0];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x40000000;
    entry.translatedAddress = 0x40000000;
    entry.size = AMMU.Large_512M;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /* map program code/data memory into ammu (cacheable) */
    var entry = AMMU.largePages[1];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x80000000;
    entry.translatedAddress = 0x80000000;
    entry.size = AMMU.Large_512M;
    entry.L1_cacheable = AMMU.CachePolicy_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_POSTED;
    entry.L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
    entry.L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    /* map SR_0 data memory into ammu (non-cacheable) */
    var entry = AMMU.largePages[2];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0xA0000000;
    entry.translatedAddress = 0xA0000000;
    entry.size = AMMU.Large_512M;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

    var entry = AMMU.largePages[3];
    entry.pageEnabled = AMMU.Enable_YES;
    entry.translationEnabled = AMMU.Enable_YES;
    entry.logicalAddress = 0x60000000;
    entry.translatedAddress = 0x40000000;
    entry.size = AMMU.Large_512M;
    entry.L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L1_posted = AMMU.PostedPolicy_NON_POSTED;
    entry.L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    entry.L2_posted = AMMU.PostedPolicy_NON_POSTED;

}

Regards,

kyungtae