CCS/AM6548: SMP debug issue

Tool/software: Code Composer Studio

Hi TI Experts,

I have a problem with SMP Debug. In the next text i will try to explain all steps i did to run SMP on TMDX654IDKEVM (SoC AM6548).

I made CCS project for SMP by using the example (TaskSetPriTest1.c and TaskSetPriTest1.cfg files) which was made by Judah

(https://e2e.ti.com/support/processors/f/791/p/798502/2956004#2956004)

In example above, the first cluster is used to run two task on two different cores (CortexA53_0_0 and CortexA53_0_1)

[Step.1]

I will start with my CCS setup:

1.  I created target configuration file (.ccxml file)
2. Then, in target configuration, I have attached the appropriate initialization scripts (GEL files) to the appropriate cores

Core = DMSC_Cortex_M3_0 --> GEL = C:\ti\ccsv8\ccs_base\emulation\boards\am65x\gel\AM65xEVM.gel
Core = MCU_PULSAR_Cortex_R5_0 --> GEL = C:\ti\ccsv8\ccs_base\emulation\boards\am65x\gel\M4_DDR39SS\M4_R5orA53_Startup.gel
Core = CortexA53_0_0 --> GEL = C:\ti\ccsv8\ccs_base\emulation\boards\am65x\gel\M4_DDR39SS\M4_R5orA53_Startup.gel
Core = CortexA53_0_1 --> GEL = C:\ti\ccsv8\ccs_base\emulation\boards\am65x\gel\M4_DDR39SS\M4_R5orA53_Startup.gel

3. Then, in debug configuration, I loaded JavaScript file from new PDK (C:\ti\pdk_am65xx_1_0_4\packages\ti\drv\sciclient\tools\ccsLoadDmsc\launch_am65xx.js)

4. I had changed JavaScript file. I set flag disableGelLoad to 1 (disableGelLoad = 1). When disableGelLoad is set to 1, debugger will take GEL files (for M3 and R5 cores) from target configuration and not from the path which are specified in JS file.

[Step.2]

Then i performed the next procedure:

1. Launch the target configuration.
2. Set two A53 cores (first cluster) as Group 1 with "Sync Group cores"
3. Connect the Group 1
4. Load the .out file in the following directory to each cores.
4-1. Load this file to A53_0_1
4-2. Load this file to A53_0_0 and this core was running the code.
5. Start the program with push the resume on A53_0_0 core.

But application execution was stuck at the beginning of the code, on _c_int00(). And the following error was printed:
------------------------------------------------------------------------------------------------
CortexA53_0_0: Trouble Halting Target CPU: (Error -2062 - (0:23:2)) Unable to halt device. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.0.903.2)

CortexA53_0_1: Trouble Halting Target CPU: (Error -2062 - (0:23:2)) Unable to halt device. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 8.0.903.2)
------------------------------------------------------------------------------------------------

According to the following wiki and docs, it seems that I need to modify the GEL file in order to run the SMP_Debug. I need to set what regions of memory are shared between the cores

Wiki: http://processors.wiki.ti.com/index.php/SMP/BIOS#Supported_devices

Docs: http://processors.wiki.ti.com/images/1/14/Public_SmpBiosSlides.pdf

I used MSMC memory to store program, and that is specified in linker file:

MEMORY
{
MSMC (RWX) : ORIGIN = 0x70000000, LENGTH = 0x00200000
DDR (RWX) : ORIGIN = 0x80000000, LENGTH = 0x80000000
}

REGION_ALIAS("REGION_TEXT", MSMC);
REGION_ALIAS("REGION_BSS", MSMC);
REGION_ALIAS("REGION_DATA", MSMC);
REGION_ALIAS("REGION_STACK", MSMC);
REGION_ALIAS("REGION_HEAP", MSMC);
REGION_ALIAS("REGION_ARM_EXIDX", MSMC);
REGION_ALIAS("REGION_ARM_EXTAB", MSMC);

So the next step was to try to set what regions of memory are shared between core A53_0_0 and core A53_0_1, that part was added in "M4_R5orA53_Startup.gel" file:
I puted the folowing code in GEL file.

memorymap_init_SMP()
{
GEL_MapAddStr(0x70000000, 0, 0x00200000, "RAM|AS8|SH1C|CACHE ", 0);
}
menuitem "Memory config"
hotmenu SMP_Config()
{
GEL_MapOff();
GEL_MapReset();
memorymap_init_SMP();
GEL_MapOn();
}

Then i repeated [Step.2] ones again, with small difference, before loading the .out file to Syns Group we must go to Scripts->Memory config->SMP_Config, and we must do that step for both cores.

The both cores are in Running state and it cannot be Halted. The following error was printed:
---------------------------------------------------------------------------
CortexA53_0_1: Trouble Setting Breakpoint with the Action "Terminate Program Execution" at 0x70014750: (Error -2002 - (0:28:4)) Internal error: Invalid parameter passed to function. Restart the application. If error persists, please report the error. (Emulation package 8.0.903.2)

CortexA53_0_0: Trouble Setting Breakpoint with the Action "Terminate Program Execution" at 0x70014750: (Error -2002 - (0:28:4)) Internal error: Invalid parameter passed to function. Restart the application. If error persists, please report the error. (Emulation package 8.0.903.2)
-----------------------------------------------------------------------------

In Docs, from processors wiki, is specified:

• Create a “Sync Group”, not a "Fixed Group", that groups the cores in the SMP sub-system.
• Go to Tools->Debugger Options->Misc/Other Options and select “Allow software breakpoints to be used”.

So i followed the all previous steps, which are described in Docs from processors wiki.

I would appreciate if you tell me how to solve this problem, because i don't have any idea how to solve this.

If you have any questions, please let me know.

Best regards,
Novica