66AK2H14: How to route event as exception for DDR protection by MPAX ?

Hi,

I saw you opened https://e2e.ti.com/support/processors/f/791/t/824496 last month and resolved it by routing interrupt 119 through 127. That code tried the invalid DDR access. What is the difference between this test case and that one?

Regards, Eric 

Hi,

My mistake sorry, I though I answer to another post about MPPA, in fact I rectified my code but I don't manage to handle exceptions..

Regards,

François

Hi,

Thanks! So for the issue you opened in this thread, are you able to attach the CCS project or source code? And explain what you expected and what is not working?

Regards, Eric

Yes of course. I attached my file in the post following this one.

In the code DSP core0 write in its DDR area (OK) and DSP core1 also (NOK).

I expected DSP core1 could not write any data (that's ok) and an exception occurred with memory protection fault registers updates (that's ok).

Once the exception occurred, I would like to handle it in a function (doesn't work).

My expectation is just a exception handle.

Thanks,

CFG:




var Defaults = xdc.useModule('xdc.runtime.Defaults');
var Diags = xdc.useModule('xdc.runtime.Diags');
var Error = xdc.useModule('xdc.runtime.Error');
var Log = xdc.useModule('xdc.runtime.Log');
var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
var Main = xdc.useModule('xdc.runtime.Main');
var Memory = xdc.useModule('xdc.runtime.Memory')
var SysMin = xdc.useModule('xdc.runtime.SysMin');
var System = xdc.useModule('xdc.runtime.System');
var Text = xdc.useModule('xdc.runtime.Text');
var Program = xdc.useModule('xdc.cfg.Program');

var BIOS = xdc.useModule('ti.sysbios.BIOS');
var Clock = xdc.useModule('ti.sysbios.knl.Clock');
var Swi = xdc.useModule('ti.sysbios.knl.Swi');
var Task = xdc.useModule('ti.sysbios.knl.Task');
var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
var Hwi = xdc.useModule('ti.sysbios.family.c64p.Hwi');
var Idle = xdc.useModule('ti.sysbios.knl.Idle');
var LoggingSetup = xdc.useModule('ti.uia.sysbios.LoggingSetup');
var ti_sysbios_hal_Core = xdc.useModule('ti.sysbios.hal.Core');
var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
var MemoryProtect = xdc.useModule('ti.sysbios.family.c64p.MemoryProtect');
var Exception = xdc.useModule('ti.sysbios.family.c64p.Exception');
var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
var Event = xdc.useModule('ti.sysbios.knl.Event');
var EventCombiner = xdc.useModule('ti.sysbios.family.c64p.EventCombiner'); 

/*
 * Uncomment this line to globally disable Asserts.
 * All modules inherit the default from the 'Defaults' module.  You
 * can override these defaults on a per-module basis using Module.common$. 
 * Disabling Asserts will save code space and improve runtime performance.
Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
 */

/*
 * Uncomment this line to keep module names from being loaded on the target.
 * The module name strings are placed in the .const section. Setting this
 * parameter to false will save space in the .const section.  Error and
 * Assert messages will contain an "unknown module" prefix instead
 * of the actual module name.
Defaults.common$.namedModule = false;
 */

/*
 * Minimize exit handler array in System.  The System module includes
 * an array of functions that are registered with System_atexit() to be
 * called by System_exit().
 */
System.maxAtexitHandlers = 4;       

/* 
 * Uncomment this line to disable the Error print function.  
 * We lose error information when this is disabled since the errors are
 * not printed.  Disabling the raiseHook will save some code space if
 * your app is not using System_printf() since the Error_print() function
 * calls System_printf().
Error.raiseHook = null;
 */

/* 
 * Uncomment this line to keep Error, Assert, and Log strings from being
 * loaded on the target.  These strings are placed in the .const section.
 * Setting this parameter to false will save space in the .const section.
 * Error, Assert and Log message will print raw ids and args instead of
 * a formatted message.
Text.isLoaded = false;
 */

/*
 * Uncomment this line to disable the output of characters by SysMin
 * when the program exits.  SysMin writes characters to a circular buffer.
 * This buffer can be viewed using the SysMin Output view in ROV.
SysMin.flushAtExit = false;
 */

/*
 * The BIOS module will create the default heap for the system.
 * Specify the size of this default heap.
 */
BIOS.heapSize = 0x1000;

/*
 * Build a custom SYS/BIOS library from sources.
 */
BIOS.libType = BIOS.LibType_Custom;

/* BIOS addons */
BIOS.mpeEnabled = true;
BIOS.taskEnabled = true;
BIOS.smpEnabled = true;

/* System stack size (used by ISRs and Swis) */
Program.stack = 0x2000;

/* Exception */
Exception.enableExternalMPC = true;
Exception.enablePrint = false;
Exception.useInternalBuffer = true; 
Exception.exceptionHook = "&myExcep_handler";
Exception.externalHook = "&myExcep_handler_extn";
Exception.internalHook = "&myExcep_handler_intn";
Exception.nmiHook = "&myExcep_handler_nmi";
Exception.returnHook = null;

/* Hw Interupt */
Hwi.enableException = true;

/* Circular buffer size for System_printf() */
SysMin.bufSize = 0x2000;

/* 
 * Create and install logger for the whole system
 */
var loggerBufParams = new LoggerBuf.Params();
loggerBufParams.numEntries = 16;
var logger0 = LoggerBuf.create(loggerBufParams);
Defaults.common$.logger = logger0;
Main.common$.diags_INFO = Diags.ALWAYS_ON;

System.SupportProxy = SysMin;

LoggingSetup.benchmarkLogging = false;

/* MemProtect Task */
var task1Params = new Task.Params();
task1Params.instance.name = "mem_protect";
task1Params.priority = 15;
task1Params.stackSize = 1024;
Program.global.mem_protect = Task.create("&mem_protectFxn", task1Params);

/* Protection Test Task */
var task2Params = new Task.Params();
task2Params.instance.name = "protection_test";
task2Params.priority = 15;
task2Params.stackSize = 1024;
Program.global.mem_protect = Task.create("&protection_testFxn", task2Params);


Program.sectMap[".kernel_heap"] 	= 	"DDR3";
Program.sectMap[".public_heap"] 	= 	"DDR3";

/*
 * @file main.c
 * @author F. Poulain
 * @date 20/08/2019
 *
 * @brief This test using MPAX registers for protecting DDR region.
 *
 * In this test DSP#0 and DSP#1 have a specific DDR region and only dedicated core to DDR region can access the region.
 *
 */

/* TI RTOS dependences */
#include <xdc/std.h>

#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <xdc/runtime/Log.h>

#include <ti/sysbios/BIOS.h>

#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Clock.h>

#include <ti/sysbios/hal/Core.h>
#include <ti/sysbios/family/c64p/Hwi.h>
#include <ti/sysbios/family/c64p/MemoryProtect.h>
#include <ti/sysbios/family/c64p/Exception.h>
#include <ti/sysbios/family/c66/Cache.h>
#include <ti/sysbios/family/c64p/EventCombiner.h>

/* C dependencies */
#include <string.h>

/* Project dependencies */
#include <func.h>

/*
 *  ======== mem_protectFxn ========
 */
Void mem_protectFxn(UArg a0, UArg a1)
{
    /* Memory Initialization */
    memory_init();

    /* Clear any previous fault */
    //CSL_XMC_clearFault();

    /* XMPAX pointed addresses */
    UInt32 *xmpaxl=NULL;
    UInt32 *xmpaxh=NULL;

    if (DNUM==0) /* DSP#0 code */
    {
        /* DDR 1st segment */
        xmpaxl = (Uint32*) XMPAXL6;
        xmpaxh = (Uint32*) XMPAXH6;

        *xmpaxl = 0x83000000 + 0xB6; // allows SR, SW, UR; UW
        *xmpaxh = 0xB0000000 + 0x17; // segz = '10111' --> 0x17 --> 16MB

        /* DDR 2nd segment */
        xmpaxl = (Uint32*) XMPAXL7;
        xmpaxh = (Uint32*) XMPAXH7;

        *xmpaxl = 0x83100000 + 0x80; // no permissions
        *xmpaxh = 0xB1000000 + 0x17; // segz = '10111' --> 0x17 --> 16MB
    }

    if (DNUM==1) /* DSP#1 code */
    {
        /* DDR 1st segment */
        xmpaxl = (Uint32*) XMPAXL6;
        xmpaxh = (Uint32*) XMPAXH6;

        *xmpaxl = 0x83000000 + 0x80; // no permissions
        *xmpaxh = 0xB0000000 + 0x17; // segz = '10111' --> 0x17 --> 16MB

        /* DDR 2nd segment */
        xmpaxl = (Uint32*) XMPAXL7;
        xmpaxh = (Uint32*) XMPAXH7;

        *xmpaxl = 0x83100000 + 0xB6; // allows SR, SW, UR; UW
        *xmpaxh = 0xB1000000 + 0x17; // segz = '10111' --> 0x17 --> 16MB
    }

    System_flush(); /* force SysMin output to console */
}

/*********************************************
 *          protection_testFxn
 *********************************************/
Void protection_testFxn(UArg a0, UArg a1)
{
    while (1)
    {
        if (DNUM==0)
        {
            memset((void*)0xB0000000, 0x10, 0x100); /* allowed access */
            //memset((void*)0xB1000000, 0x20, 0x100); /* violation access */
        }

        if (DNUM==1)
        {
            memset((void*)0xB0000000, 0x11, 0x100); /* violation access */
            //memset((void*)0xB1000000, 0x21, 0x100); /* allowed access */
        }

        System_flush(); /* force SysMin output to console */
    }
}

/*
 *  ======== main ========
 */
Int main()
{
    System_printf("enter main()\n");

    /* Routing event 119 through 127 to DSP core as exception */
    UInt32 i=0;

    Exception_evtExpMaskEnable(10);
    for (i=102; i<110; i++)
    {
        Exception_evtExpMaskEnable(i);
    }
    for (i=119; i<128; i++)
    {
        Exception_evtExpMaskEnable(i);
    }

    BIOS_start();    /* does not return */
    return(0);
}

/*
 * @file func.c
 * @author F. Poulain
 * @date 20/08/2019
 *
 * @brief This file contains API and exception handlers
 *
 */

/* Project dependencies */
#include <func.h>

/*
 * @brief Initialize memory
 * @param Void
 * @return Void
 */
Void memory_init(Void)
{
    UInt32 k=0;
    UInt8 pcx; /* reserved bit, do not touch */
    UInt8 pfx; /* prefetchability */

    /* Set DDR as non-cacheable */
    for (k=128; k<=255; k++)
    {
        CACHE_disableCaching(k);                    /* Set PC at '0' */
        CACHE_getMemRegionInfo (k, &pcx, &pfx);     /* get memory region information */
        pfx = 1;                                    /* enable prefetch */
        CACHE_setMemRegionInfo(k, pcx, pfx);        /* set memory region information */
    }

    /* Cache initialization */
    CACHE_setL2Size(CACHE_0KCACHE);
    CACHE_setL1DSize(CACHE_L1_32KCACHE);
    CACHE_setL1PSize(CACHE_L1_32KCACHE);
}

/*
 * @brief Decode MPFSR register
 * @param UInt32 MPFSR register
 * @return Void
 */
Void error_decode_mpfsr(UInt32 mpfsr)
{
    if ((mpfsr & MPFSR_LOCAL) != 0)
    {
        System_printf( "Security violation, Local L1/L2 cache memory Fault\n");
    }
    if ((mpfsr & MPFSR_SECE) != 0)
    {
        System_printf( "Security violation, Fault ID=0x%x\n",
            (mpfsr & MPFSR_FIDMASK) >> MPFSR_FIDSHIFT);
    }
    if ((mpfsr & MPFSR_UXE) != 0)
    {
        System_printf( "User Execute violation, Fault ID=0x%x\n",
            (mpfsr & MPFSR_FIDMASK) >> MPFSR_FIDSHIFT);
    }
    if ((mpfsr & MPFSR_UWE) != 0)
    {
        System_printf( "User Write violation, Fault ID=0x%x\n",
            (mpfsr & MPFSR_FIDMASK) >> MPFSR_FIDSHIFT);
    }
    if ((mpfsr & MPFSR_URE) != 0)
    {
        System_printf( "User Read violation, Fault ID=0x%x\n",
            (mpfsr & MPFSR_FIDMASK) >> MPFSR_FIDSHIFT);
    }
    if ((mpfsr & MPFSR_SXE) != 0)
    {
        System_printf( "Supervisor Excecute violation, Fault ID=0x%x\n",
            (mpfsr & MPFSR_FIDMASK) >> MPFSR_FIDSHIFT);
    }
    if ((mpfsr & MPFSR_SWE) != 0)
    {
        System_printf( "Supervisor Write violation, Fault ID=0x%x\n",
            (mpfsr & MPFSR_FIDMASK) >> MPFSR_FIDSHIFT);
    }
    if ((mpfsr & MPFSR_SRE) != 0)
    {
        System_printf( "Supervisor Read violation, Fault ID=0x%x\n",
            (mpfsr & MPFSR_FIDMASK) >> MPFSR_FIDSHIFT);
    }
}

/*
 * @brief Decode XMPFSR register
 * @param UInt32 XMPFAR register
 * @param CSL_XMC_MPFSR XMPFSR register
 * @return Void
 */
Void error_decode_xmpfsr(UInt32 faultAddr, CSL_XMC_MPFSR xmpfsr)
{
    if (xmpfsr.local != 0)
        System_printf("Local L1/L2 cache memory violation at : 0x%x\n", faultAddr);

    if (xmpfsr.sr != 0)
        System_printf("Supervisor Read violation at : 0x%x\n", faultAddr);

    if (xmpfsr.sw != 0)
        System_printf("Supervisor Write violation at : 0x%x\n", faultAddr);

    if (xmpfsr.sx != 0)
        System_printf("Supervisor eXecute violation at : 0x%x\n", faultAddr);

    if (xmpfsr.ur != 0)
        System_printf("User Read violation at : 0x%x\n", faultAddr);

    if (xmpfsr.uw != 0)
        System_printf("User Write violation at : 0x%x\n", faultAddr);

    if (xmpfsr.ux != 0)
        System_printf("User eXecute violation at : 0x%x\n", faultAddr);
}

/*
 * @brief Handler for OS exception
 * @param Void
 * @return Void
 */
Void myExcep_handler(Void)
{
    Exception_Status status;
    Exception_getLastStatus(&status);
    System_printf("Operating System Exception detected. Program counter (NRP) = 0x%x\n", status.nrp);
}

/*
 * @brief Handler for external exception
 * @param Void
 * @return Void
 */
Void myExcep_handler_extn(Void)
{
    System_printf("External Exception occurred\n");

    UInt32 xmpfar;
    CSL_XMC_MPFSR xmpfsr;

    xmpfar = CSL_XMC_getFaultAddress();

    if (xmpfar != 0)
    {
        CSL_XMC_getFaultStatus (&xmpfsr);
        error_decode_xmpfsr(xmpfar, xmpfsr);
    }

    if (*PMC_MPFSR != 0)
    {
        System_printf("PMC Exception MPFAR=0x%x MPFSR=0x%x\n", *PMC_MPFAR, *PMC_MPFSR);
        error_decode_mpfsr(*PMC_MPFSR);
        *PMC_MPFCR = 1;
    }

    if (*DMC_MPFSR != 0)
    {
        System_printf("DMC Exception MPFAR=0x%x MPFSR=0x%x\n", *DMC_MPFAR, *DMC_MPFSR);
        error_decode_mpfsr(*DMC_MPFSR);
        *DMC_MPFCR = 1;
    }

    if (*UMC_MPFSR != 0)
    {
        System_printf("UMC Exception MPFAR=0x%x MPFSR=0x%x\n", *UMC_MPFAR, *UMC_MPFSR);
        error_decode_mpfsr(*UMC_MPFSR);
        *UMC_MPFCR = 1;
    }
}

/*
 * @brief Handler for internal exception
 *
 * @param Void
 * @return Void
 */
Void myExcep_handler_intn(Void)
{
    Exception_Status status;
    Exception_getLastStatus(&status);

    System_printf("Exception type: Internal IERR=0x%x\n", status.ierr);

    if ((status.ierr & Exception_IERRIFX) != 0)
    {
        System_printf("Instruction fetch exception\n");
    }
    if ((status.ierr & Exception_IERRFPX) != 0)
    {
        System_printf("Fetch packet exception\n");
    }
    if ((status.ierr & Exception_IERREPX) != 0)
    {
        System_printf("Execute packet exception\n");
    }
    if ((status.ierr & Exception_IERROPX) != 0)
    {
        System_printf("Opcode exception\n");
    }
    if ((status.ierr & Exception_IERRRCX) != 0)
    {
        System_printf("Resource conflict exception\n");
    }
    if ((status.ierr & Exception_IERRRAX) != 0)
    {
        System_printf("Resource access exception\n");
    }
    if ((status.ierr & Exception_IERRPRX) != 0)
    {
        System_printf("Privilege exception\n");
    }
    if ((status.ierr & Exception_IERRLBX) != 0)
    {
        System_printf("Loop buffer exception\n");
    }
    if ((status.ierr & Exception_IERRMSX) != 0)
    {
        System_printf("Missed stall exception\n");
    }
}

/*
 * @brief Handler for non-maskeable interrupt
 * @param Void
 * @return Void
 */
Void myExcep_handler_nmi(Void)
{
    System_printf("Exception type: Legacy Non-Maskable Interrupt detected \n");
}

/*
 * @file func.h
 * @author F. Poulain
 * @date 20/08/2019
 *
 * @brief Header file for API and exception handlers
 *
 */

#ifndef INCLUDES_FUNC_H_
#define INCLUDES_FUNC_H_

/* TI RTOS dependencies */
#include <xdc/std.h>

#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
#include <xdc/runtime/Log.h>

#include <ti/sysbios/BIOS.h>

#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Clock.h>

#include <ti/sysbios/hal/Core.h>
#include <ti/sysbios/family/c64p/Hwi.h>
#include <ti/sysbios/family/c64p/MemoryProtect.h>
#include <ti/sysbios/family/c64p/Exception.h>
#include <ti/sysbios/family/c66/Cache.h>

/* TI dependencies */
#include <c6x.h>
#include <csl_xmc.h>
#include <csl_xmcAux.h>
#include <csl_cache.h>
#include <csl_cacheAux.h>

/* C dependencies */
#include <string.h>

/* MPAX registers addresses */
#define XMPAXL6     (0x08000030)
#define XMPAXH6     (0x08000034)
#define XMPAXL7     (0x08000038)
#define XMPAXH7     (0x0800003C)

/* XMC Memory Protection Fault Registers */
#define XMPFAR (UInt32 *)0x08000200
#define XMPFSR (UInt32 *)0x08000204
#define XMPFCR (UInt32 *)0x08000208

/* Memory Protection Fault Registers */
#define UMC_MPFAR (UInt32 *)0x0184A000
#define UMC_MPFSR (UInt32 *)0x0184A004
#define UMC_MPFCR (UInt32 *)0x0184A008
#define PMC_MPFAR (UInt32 *)0x0184A400
#define PMC_MPFSR (UInt32 *)0x0184A404
#define PMC_MPFCR (UInt32 *)0x0184A408
#define DMC_MPFAR (UInt32 *)0x0184AC00
#define DMC_MPFSR (UInt32 *)0x0184AC04
#define DMC_MPFCR (UInt32 *)0x0184AC08

/* For decoding Memory Protection Fault Registers */
#define MPPA_UX         0x00000001      // User eXecute
#define MPPA_UW         0x00000002      // User Write
#define MPPA_UR         0x00000004      // User Read
#define MPPA_SX         0x00000008      // Supervisor eXecute
#define MPPA_SW         0x00000010      // Supervisor Write
#define MPPA_SR         0x00000020      // Supervisor Read
#define MPPA_LOCAL      0x00000100      // LOCAL CPU access
#define MPFSR_UXE       MPPA_UX
#define MPFSR_UWE       MPPA_UW
#define MPFSR_URE       MPPA_UR
#define MPFSR_SXE       MPPA_SX
#define MPFSR_SWE       MPPA_SW
#define MPFSR_SRE       MPPA_SR
#define MPFSR_LOCAL     MPPA_LOCAL
#define MPFSR_SECE      0x00000080
#define MPFSR_FIDMASK   0x0000FE00
#define MPFSR_FIDSHIFT  9

/* API */

/*
 * @brief Initialize memory
 *
 * This function set DDR as non-cacheable.
 *
 * @param Void
 * @return Void
 */
Void memory_init(Void);

/*
 * @brief Decode MPFSR register
 *
 * This function decode MPSFR register for easy user read.
 *
 * @param UInt32 MPFSR register
 * @return Void
 */
Void error_decode_mpfsr(UInt32 mpfsr);

/*
 * @brief Decode XMPFSR register
 *
 * This function decode XMPFSR register for easy user read.
 *
 * @param UInt32 XMPFAR register
 * @param CSL_XMC_MPFSR XMPFSR register
 * @return Void
 */
Void error_decode_xmpfsr(UInt32 faultAddr, CSL_XMC_MPFSR xmpfsr);


/* Handler for exception */

/*
 * @brief Handler for OS exception
 *
 * @param Void
 * @return Void
 */
Void myExcep_handler(Void);

/*
 * @brief Handler for external exception
 *
 * @param Void
 * @return Void
 */
Void myExcep_handler_extn(Void);

/*
 * @brief Handler for internal exception
 *
 * @param Void
 * @return Void
 */
Void myExcep_handler_intn(Void);

/*
 * @brief Handler for non-maskeable interrupt
 *
 * @param Void
 * @return Void
 */
Void myExcep_handler_nmi(Void);

#endif /* INCLUDES_FUNC_H_ */

Hi Eric,

If I refer to

for the range 0x0C00 0000 - 0xFFFF FFFF, the corresponding events are 10 and 110, I used it but no exception generation.

I also trying to use INTC0 for MSMC by using the example Table 9.

That gives:

/* Routing event to DSP core as exception */
    UInt32 i=0;

    Exception_evtExpMaskEnable(10);
    Exception_evtEvtClear(110);
    Exception_evtExpMaskEnable(110);


    /* INTC */
    CpIntc_enableAllHostInts(0);

    for (i=170; i<174; i++)
    {
        CpIntc_mapSysIntToHostInt(0, i,  64);
        CpIntc_enableSysInt(0, i);
    }
    CpIntc_enableHostInt(0, 64);

    for (i=102; i<110; i++)
    {
        CpIntc_mapSysIntToHostInt(0, i,  65);
        CpIntc_enableSysInt(0, i);
    }
    CpIntc_enableHostInt(0, 65);

Hi,

I was not able to build your test case with the source codes grouped together, I got linking error:

**** Build of configuration Debug for project MPU_C66x ****

"C:\\ti\\ccs_8_3_0\\ccsv8\\utils\\bin\\gmake" -k -j 8 all -O

Building file: "../app.cfg"
Invoking: XDCtools
"C:/ti/ccs_8_3_0/xdctools_3_51_01_18_core/xs" --xdcpath="C:/ti/bios_6_75_02_00/packages;" xdc.tools.configuro -o configPkg -t ti.targets.elf.C66 -p ti.platforms.evmTCI6636K2H -r release -c "C:/ti/ti-cgt-c6000_8.3.2" --compileOptions "-g" "../app.cfg"
making package.mak (because of package.bld) ...
generating interfaces for package configPkg (because package/package.xdc.inc is older than package.xdc) ...
configuring app.xe66 from package/cfg/app_pe66.cfg ...
generating custom ti.sysbios library makefile ...
Starting build of library sources ...
making C:/Project/MPU_C66x/src/sysbios/sysbios.ae66 ...
cle66 C:/ti/bios_6_75_02_00/packages/ti/sysbios/BIOS.c ...
asme66 C:/ti/bios_6_75_02_00/packages/ti/sysbios/family/c64p/Exception_asm.s64P ...
asme66 C:/ti/bios_6_75_02_00/packages/ti/sysbios/family/c64p/Hwi_asm.s62 ...
asme66 C:/ti/bios_6_75_02_00/packages/ti/sysbios/family/c64p/Hwi_asm_switch.s62 ...
asme66 C:/ti/bios_6_75_02_00/packages/ti/sysbios/family/c64p/Hwi_disp_always.s64P ...
asme66 C:/ti/bios_6_75_02_00/packages/ti/sysbios/family/c64p/MemoryProtect_asm.s64P ...
asme66 C:/ti/bios_6_75_02_00/packages/ti/sysbios/rts/ti/tls_get_tp.asm ...
asme66 C:/ti/bios_6_75_02_00/packages/ti/sysbios/family/c62/TaskSupport_asm.s62 ...
asme66 C:/ti/bios_6_75_02_00/packages/ti/sysbios/timers/timer64/Timer_asm.s64P ...
are66 BIOS.obj c64p_Exception_asm.obj c64p_Hwi_asm.obj c64p_Hwi_asm_switch.obj c64p_Hwi_disp_always.obj c64p_MemoryProtect_asm.obj ti_tls_get_tp.obj c62_TaskSupport_asm.obj timer64_Timer_asm.obj ...
Build of libraries done.
cle66 package/cfg/app_pe66.c ...
"C:/ti/bios_6_75_02_00/packages/ti/sysbios/knl/Task_smp.c", line 376: remark #2142-D: comparison between signed and unsigned operands
Finished building: "../app.cfg"

1 file(s) copied.
making ../src/sysbios/sysbios.ae66 ...
gmake[1]: Nothing to be done for 'all'.
Building file: "../main.c"
Invoking: C6000 Compiler
"C:/ti/ti-cgt-c6000_8.3.2/bin/cl6x" -mv6600 --include_path="C:/ti/pdk_k2hk_4_0_13/packages/ti/csl" --include_path="C:/ti/pdk_k2hk_4_0_13/packages" --include_path="C:/Project/MPU_C66x" --include_path="C:/ti/bios_6_75_02_00/packages/ti/posix/ccs" --include_path="C:/ti/ti-cgt-c6000_8.3.2/include" --define=SOC_K2H -g --diag_warning=225 --diag_wrap=off --display_error_number --preproc_with_compile --preproc_dependency="main.d_raw" --cmd_file="configPkg/compiler.opt" "../main.c"
"C:/Project/MPU_C66x/func.h", line 150: warning #1-D: last line of file ends without a newline
Finished building: "../main.c"

Building file: "../func.c"
Invoking: C6000 Compiler
"C:/ti/ti-cgt-c6000_8.3.2/bin/cl6x" -mv6600 --include_path="C:/ti/pdk_k2hk_4_0_13/packages/ti/csl" --include_path="C:/ti/pdk_k2hk_4_0_13/packages" --include_path="C:/Project/MPU_C66x" --include_path="C:/ti/bios_6_75_02_00/packages/ti/posix/ccs" --include_path="C:/ti/ti-cgt-c6000_8.3.2/include" --define=SOC_K2H -g --diag_warning=225 --diag_wrap=off --display_error_number --preproc_with_compile --preproc_dependency="func.d_raw" --cmd_file="configPkg/compiler.opt" "../func.c"
"C:/Project/MPU_C66x/func.h", line 150: warning #1-D: last line of file ends without a newline
Finished building: "../func.c"

making ../src/sysbios/sysbios.ae66 ...
gmake[2]: Nothing to be done for 'all'.
Building target: "MPU_C66x.out"
Invoking: C6000 Linker
"C:/ti/ti-cgt-c6000_8.3.2/bin/cl6x" -mv6600 --define=SOC_K2H -g --diag_warning=225 --diag_wrap=off --display_error_number -z -m"MPU_C66x.map" -i"C:/ti/ti-cgt-c6000_8.3.2/lib" -i"C:/ti/ti-cgt-c6000_8.3.2/include" --reread_libs --diag_wrap=off --display_error_number --warn_sections --xml_link_info="MPU_C66x_linkInfo.xml" --rom_model -o "MPU_C66x.out" "./func.obj" "./main.obj" -l"configPkg/linker.cmd" -llibc.a
<Linking>

undefined first referenced
symbol in file
--------- ----------------
ti_sysbios_hal_Hwi_disable__E C:\Project\MPU_C66x\src\sysbios\sysbios.ae66<BIOS.obj>
ti_sysbios_hal_Hwi_enable__E C:\Project\MPU_C66x\src\sysbios\sysbios.ae66<BIOS.obj>
ti_sysbios_hal_Hwi_restore__E C:\Project\MPU_C66x\src\sysbios\sysbios.ae66<BIOS.obj>

error #10234-D: unresolved symbols remain
error #10010: errors encountered during linking; "MPU_C66x.out" not built

>> Compilation failure
makefile:141: recipe for target 'MPU_C66x.out' failed
gmake[1]: *** [MPU_C66x.out] Error 1
makefile:137: recipe for target 'all' failed
gmake: *** [all] Error 2

**** Build Finished ****

Then, I looked at your ISR setup code, does this sequence work for mapping any other system interrupt to host? I saw a lots of API call missing, attached is a PCIE interrupt we configured (for C6678, just look at the API call sequence), you can refer to 

/************************************************
*************** INTC Configuration *************
************************************************/
write_uart("Debug: GEM-INTC Configuration...\n\r");

/* INTC module initialization */
intcContext.eventhandlerRecord = EventHandler;
intcContext.numEvtEntries = 10;
if (CSL_intcInit(&intcContext) != CSL_SOK)
{
write_uart("Error: GEM-INTC initialization failed n\r");
return;
}

/* Enable NMIs */
if (CSL_intcGlobalNmiEnable() != CSL_SOK)
{
write_uart("Error: GEM-INTC global NMI enable failed n\r");
return;
}

/* Enable global interrupts */
if (CSL_intcGlobalEnable(&state) != CSL_SOK)
{
write_uart("Error: GEM-INTC global enable failed \n\r");
return;
}

/* Open the INTC Module for Vector ID: 4 and Event ID: 63 (C6678) 59 (C6670)
* Refer to the interrupt architecture and mapping document for the Event ID (INTC0_OUT3)*/
vectId = CSL_INTC_VECTID_4;
hTest = CSL_intcOpen (&intcObj, INTC0_OUT3, &vectId , NULL);
if (hTest == NULL)
{
write_uart("Error: GEM-INTC Open failed\n\r");
return;
}

/* Register an call-back handler which is invoked when the event occurs. */
EventRecord.handler = &test_isr_handler;
EventRecord.arg = 0;
if (CSL_intcPlugEventHandler(hTest,&EventRecord) != CSL_SOK)
{
write_uart("Error: GEM-INTC Plug event handler failed\n\r");
return;
}

/* Enabling the events. */
if (CSL_intcHwControl(hTest,CSL_INTC_CMD_EVTENABLE, NULL) != CSL_SOK)
{
write_uart("Error: GEM-INTC CSL_INTC_CMD_EVTENABLE command failed\n\r");
return;
}

write_uart("Debug: GEM-INTC Configuration Completed \n\r");

/**************************************************
************* CPINTC-0 Configuration *************
**************************************************/

write_uart("Debug: CPINTC-0 Configuration...\n\r");

/* Open the handle to the CPINT Instance */
hnd = CSL_CPINTC_open(0);
if (hnd == 0)
{
write_uart("Error: Unable to open CPINTC-0\n\r");
return;
}

/* Disable all host interrupts. */
CSL_CPINTC_disableAllHostInterrupt(hnd);

/* Configure no nesting support in the CPINTC Module. */
CSL_CPINTC_setNestingMode (hnd, CPINTC_NO_NESTING);

/* We now map System Interrupt 0 - 3 to channel 3 */
CSL_CPINTC_mapSystemIntrToChannel (hnd, PCIEXpress_Legacy_INTA, 3);

/* We now enable system interrupt 0 - 3 */
CSL_CPINTC_enableSysInterrupt (hnd, PCIEXpress_Legacy_INTA);

/* We enable host interrupts. */
CSL_CPINTC_enableHostInterrupt (hnd, 3);

/* Enable all host interrupts also. */
CSL_CPINTC_enableAllHostInterrupt(hnd);

Regards, Eric

/******************************************************************************
* Copyright (c) 2011 Texas Instruments Incorporated - http://www.ti.com
*
*  Redistribution and use in source and binary forms, with or without
*  modification, are permitted provided that the following conditions
*  are met:
*
*    Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
*
*    Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the
*    distribution.
*
*    Neither the name of Texas Instruments Incorporated emac the names of
*    its contributors may be used to endorse or promote products derived
*    from this software without specific prior written permission.
*
*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/

/**************************************************************************************
* FILE PURPOSE: PCIe Boot Interrupt Example
**************************************************************************************
* FILE NAME: pcieboot_interrupt.c
*
* DESCRIPTION: A simple interrupt example demonstrating PCIe boot.
*
***************************************************************************************/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "platform.h"

#include <ti/csl/src/intc/csl_intc.h>
#include <ti/csl/tistdtypes.h>
#include <ti/csl/csl_cpIntcAux.h>

#define DEVICE_REG32_W(x,y)   *(volatile uint32_t *)(x)=(y)
#define DEVICE_REG32_R(x)    (*(volatile uint32_t *)(x))

#define DDR_TEST_START                 0x80000000
#define DDR_TEST_END                   0x80400000
#define BOOT_UART_BAUDRATE                 115200
#define PCIEXpress_Legacy_INTA                 50
#define PCIE_IRQ_EOI                   0x21800050
#define PCIE_EP_IRQ_SET		           0x21800064
#define PCIE_LEGACY_A_IRQ_STATUS       0x21800184

#ifdef _EVMC6678L_
#define MAGIC_ADDR     0x87fffc
#define INTC0_OUT3     63 
#endif

#ifdef _EVMC6670L_
#define MAGIC_ADDR     0x8ffffc
#define INTC0_OUT3     59 
#endif

/**********************************************************************
 ************************** Global Variables **************************
 **********************************************************************/
/* Intc variable declaration */
CSL_CPINTC_Handle           hnd;
CSL_IntcContext             intcContext;
CSL_IntcEventHandlerRecord  EventHandler[30];
CSL_IntcObj                 intcObj;
CSL_IntcHandle              hTest;
CSL_IntcGlobalEnableState   state;
CSL_IntcEventHandlerRecord  EventRecord;
CSL_IntcParam               vectId;

uint32_t counter = 0;

void write_uart(char* msg)
{
    uint32_t i;
    uint32_t msg_len = strlen(msg);

    /* Write the message to the UART */
    for (i = 0; i < msg_len; i++)
    {
        platform_uart_write(msg[i]);
    }
}

void start_boot(void)
{
    void (*exit)();
    uint32_t entry_addr;

    /* Clear the boot entry address */
    DEVICE_REG32_W(MAGIC_ADDR, 0);

    while(1)
    {
        entry_addr = DEVICE_REG32_R(MAGIC_ADDR);
        if (entry_addr != 0)
        {
            /* jump to the exit point, which will be the entry point for the full IBL */
            exit = (void (*)())entry_addr;
            (*exit)();
        }
        platform_delay(1);
    }
}

/**********************************************************************
 ************************ CPINTC TEST FUNCTIONS ***********************
 **********************************************************************/

/**
 *  @b Description
 *  @n
 *      This is the TEST ISR Handler which has been installed.
 *      This simply increments a global variable which counts
 *      the number of interrupts which have been received.
 *
 *  @retval
 *      Not Applicable.
 */
static void test_isr_handler(void* handle)
{
	uint32_t i;

	counter++;
	printf    ("DSP receives interrupt from host.\n");
	write_uart("DSP receives interrupt from host.\n\r");

	/* Disable host interrupt */
	CSL_CPINTC_disableHostInterrupt (hnd, 3);

    /* do a simple operation in the DDR data */
    for (i = DDR_TEST_START; i < DDR_TEST_END; i += 4)
		*(uint32_t *)i = ~(*(uint32_t *)i);
	
	/* clear PCIE interrupt */
    DEVICE_REG32_W(PCIE_LEGACY_A_IRQ_STATUS, 0x1);
    DEVICE_REG32_W(PCIE_IRQ_EOI, 0x0);
    CSL_CPINTC_clearSysInterrupt (hnd, PCIEXpress_Legacy_INTA);

    /* Enable host interrupt */
    CSL_CPINTC_enableHostInterrupt (hnd, 3);

    /* generate interrupt to host */
	*((uint32_t *)PCIE_EP_IRQ_SET) = 0x1;
	printf    ("DSP generates interrupt to host.\n");
	write_uart("DSP generates interrupt to host.\n\r");
}	

/* OSAL functions for Platform Library */
uint8_t *Osal_platformMalloc (uint32_t num_bytes, uint32_t alignment)
{
	return malloc(num_bytes);
}

void Osal_platformFree (uint8_t *dataPtr, uint32_t num_bytes)
{
    /* Free up the memory */
    if (dataPtr)
    {
        free(dataPtr);
    }
}

void Osal_platformSpiCsEnter(void)
{
    return;
}

void Osal_platformSpiCsExit (void)
{
    return;
}

/**
 *  @b Description
 *  @n
 *      Entry point for the test code.
 *
 *  @retval
 *      Not Applicable.
 */
void main (void)
{
	platform_init_flags     init_flags;
    platform_init_config    init_config;

    /* Initialize main Platform lib */
    memset(&init_config, 0, sizeof(platform_init_config));
    memset(&init_flags, 1, sizeof(platform_init_flags));

    platform_init(&init_flags, &init_config);

	/* Initialize UART */
	platform_uart_init();
    platform_uart_set_baudrate(BOOT_UART_BAUDRATE);

    DEVICE_REG32_W(MAGIC_ADDR, 0);
    DEVICE_REG32_W(PCIE_LEGACY_A_IRQ_STATUS, 0x1);

    /************************************************
     *************** INTC Configuration *************
     ************************************************/
    write_uart("Debug: GEM-INTC Configuration...\n\r");

    /* INTC module initialization */
    intcContext.eventhandlerRecord = EventHandler;
    intcContext.numEvtEntries      = 10;
    if (CSL_intcInit(&intcContext) != CSL_SOK)
    {
        write_uart("Error: GEM-INTC initialization failed n\r");
        return;
    }

    /* Enable NMIs */
    if (CSL_intcGlobalNmiEnable() != CSL_SOK)
    {
    	write_uart("Error: GEM-INTC global NMI enable failed n\r");
        return;
    }

    /* Enable global interrupts */
    if (CSL_intcGlobalEnable(&state) != CSL_SOK)
    {
    	write_uart("Error: GEM-INTC global enable failed \n\r");
        return;
    }

    /* Open the INTC Module for Vector ID: 4 and Event ID: 63 (C6678) 59 (C6670)
     * 	Refer to the interrupt architecture and mapping document for the Event ID  (INTC0_OUT3)*/
    vectId = CSL_INTC_VECTID_4;
    hTest = CSL_intcOpen (&intcObj, INTC0_OUT3, &vectId , NULL);
    if (hTest == NULL)
    {
    	write_uart("Error: GEM-INTC Open failed\n\r");
        return;
    }

    /* Register an call-back handler which is invoked when the event occurs. */
    EventRecord.handler = &test_isr_handler;
    EventRecord.arg = 0;
    if (CSL_intcPlugEventHandler(hTest,&EventRecord) != CSL_SOK)
    {
    	write_uart("Error: GEM-INTC Plug event handler failed\n\r");
        return;
    }

    /* Enabling the events. */
    if (CSL_intcHwControl(hTest,CSL_INTC_CMD_EVTENABLE, NULL) != CSL_SOK)
    {
    	write_uart("Error: GEM-INTC CSL_INTC_CMD_EVTENABLE command failed\n\r");
        return;
    }

    write_uart("Debug: GEM-INTC Configuration Completed \n\r");

    /**************************************************
     ************* CPINTC-0 Configuration *************
     **************************************************/

    write_uart("Debug: CPINTC-0 Configuration...\n\r");

    /* Open the handle to the CPINT Instance */
    hnd = CSL_CPINTC_open(0);
    if (hnd == 0)
    {
    	write_uart("Error: Unable to open CPINTC-0\n\r");
        return;
    }

    /* Disable all host interrupts. */
    CSL_CPINTC_disableAllHostInterrupt(hnd);

    /* Configure no nesting support in the CPINTC Module. */
    CSL_CPINTC_setNestingMode (hnd, CPINTC_NO_NESTING);

   	/* We now map System Interrupt 0 - 3 to channel 3 */
  	CSL_CPINTC_mapSystemIntrToChannel (hnd, PCIEXpress_Legacy_INTA, 3);

   	/* We now enable system interrupt 0 - 3 */
   	CSL_CPINTC_enableSysInterrupt (hnd, PCIEXpress_Legacy_INTA);

   	/* We enable host interrupts. */
   	CSL_CPINTC_enableHostInterrupt (hnd, 3);

   	/* Enable all host interrupts also. */
   	CSL_CPINTC_enableAllHostInterrupt(hnd);

   	write_uart("Debug: CPINTC-0 Configuration Completed\n\r");

    start_boot();
}

I am not at my office until Monday, I'll get back to you on Monday.

Thanks for your answer,

Regards,

François

Hi Eric,

I don't understand why you can't link the file I sent you.. In my computer, I don't have issues, it seems if I look into your logs that

var Hwi = xdc.useModule('ti.sysbios.family.c64p.Hwi'); is not define.

Also I tried to use the code you sent me last week, for the moment, it don't work for me (I don't handle interruption). I will try to find a way to make it works in the week, I send you information when I found, issue.

Best Regards,

François

Just ti be sure:

In sprugw0c documentation p147, it says:

To enable programs to diagnose a memory protection fault after an exception occurs,
the XMC implements two registers (XMPFAR and XMPFSR) dedicated to storing
information about the fault, and a third register (XMPFCR) to allow clearing the fault
information.

In my understanding, if  XMPFAR and XMPFSR are update by the fault, the exception occured. Am I right ?

Considering if DSP core1 doing a violation access, its XMPFAR and XMPFSR register are update, and DSP core0, the victim has no updates.

In my understanding, the DSP core1 responsible for the fault recieve an exception and could not write (It is the opposite of MPPA protection mechanism). Am I right ?

I am suprised, during execution, DSP core1 is not halt when violation. In my case I really wonder if an exception occured. I tried different methods to route events as exception to DSP core, and no one works, I think I have something I don't understand.

Regards,

Hi,

"I don't understand why you can't link the file I sent you.. In my computer, I don't have issues, it seems if I look into your logs that". Why you just zip your CCS project and send me as a whole? I tired to copy and paste your code into C files and header files and created a CCS project and it is not efficient. 

I expected that XMPFAR and XMPFSR of core 1 recorded the invalid access information and an exception send to core 1.

Regards, Eric

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/sysbios_5F00_mpax_5F00_test_5F00_2cores.7z

Hi Eric,

I am currently in internship, I'll finish my job tomorrow, I would have no more access to evaluation board for test, so if we couldn't find a solution until tomorrow may be a collegue would take suite of this discussion.

Regards,

François

Thank you so much Eric !!

Regards,

François

Hi Eric

I reproduced the behavior you saw with the "clear" code: it's working as expected.

François was close! He'll be happy to know it works now.

Thanks for your help

Regards