• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 531 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C6654: EDMA3 transfer started by event on gpio18

Gildas ROLLAND
Intellectual 540 points
Part Number: TMS320C6654
Other Parts Discussed in Thread: SYSBIOS

Hi,

My project is running on TMS320C6654 with sysbios 6.76.02.02, xdctools 3.51.03.28, edma lld 02.11.09.08.

I have an interrupt configured on gpio 18. In the associated sub-routine, I manually start a dma transfer and wait its completion to process transfered data. It's working well but I want to optimize this:
- gpio 18 trigger dma transfer
- gpio 18 continue to generate interrupt which wait end of transfer and process data

On edma configuration, I have replace EDMA3_DRV_DMA_CHANNEL_ANY by EDMA3_DRV_HW_CHANNEL_EVENT_43 in EDMA3_DRV_requestChannel. 43 is the event number for CIC1_OUT0.
after edma configuration completion I execute EDMA3_DRV_enableTransfer with EDMA3_DRV_TRIG_MODE_EVENT

On CIC configuration, I have configured event 19 of CIC1 for GPINT18
 CpIntc_mapSysIntToHostInt(1, 19, 0);
 CpIntc_enableHostInt(1, 0);
 CpIntc_enableSysInt(1, 19);
 params.eventId = CpIntc_getEventId(0);
 params.arg = 0;
 Hwi_create(13, &CpIntc_dispatch, &params, &eb);
I don't have configured CpIntc_dispatch as I just want to trigger transfer. I also don't know if Hwi_create is needed or not in this case.

I have kept my configuration of CIC0 for GPINT8 unchanged, and in the subroutine I call EDMA3_DRV_waitAndClearTcc.

My program is stucked in this wait as no event seems to have occured on edma

What is wrong in my configuration?
I've read lot of e2e threads or TI documentation but did'nt find solution to my issue.

Thanks for your help

  • 0
    Guru 13202 points

    Hello!

    It seems you're on the right track. EDMA is driven by CIC1, thus you reroute gpio18 to it. To my understanding, there is no need to create event for that event.

    On the other hand, it's unclear to me what is meaning of "gpio 18 continue to generate interrupt which wait end of transfer and process data". Because EDMA can trigger interrupts as well, I would bind processing routine to EDMA transfer completion interrupt. SO basically the scheme looks like gpio18 triggers EDMA transfer without processor intervention, then upon transfer completion EDMA posts interrupt for data processing ISR. This assumes, that EDMA transfer is configured before being triggered. If that's not a case, you may still have an ISR for GPIO18 to configure and trigger the transfer. Either way, someone have to configure respective PaRAMs, enable appropriate events and interrupts etc.

  • 0 in reply to Victor Kazmirenko
    Intellectual 540 points

    Hi,

    I have data to pre-processed during dma transfer. So I want to have both edma transfer triggered by gpio18 and interrupt on gpio 18.

    In the interrupt I'll pre-process data, then call EDMA3_DRV_waitAndClearTcc to wait end of transfer for full process.

    Its' why I have kept my interrupt on gpio 18 and want to add event generation for edma transfer. I have configured first transfer during edma configuration and plan to reconfigure it in each gpio 18 interrupt

    Do you have an idea why the event is not occured?

    Regards

  • 0 in reply to Gildas ROLLAND
    Intellectual 540 points

    Hi,

    I reach to have 0x800 in edma.iprh (corresponding to event 43) in my first interrupt, so my configuration seems to be OK and first transfer should have occured (I haven't check data). But in the second interrupt, edma.iprh is 0.

    Do I miss to aknowledge something?
    Event 43 is still enabled in edma.eerh and I have no error in edma.emrh, so if something is missing I suppose it's on CIC1 side.

    Thanks for your help

  • 0 in reply to Gildas ROLLAND
    TI__Guru* 95265 points

    Hi,

    For C665x, the GPIO18 is system interrupt 19 for CIC1. The CIC1_OUT0 (43) is the input to the EDMA. If you have IPRH = 0x800, that is bit 43 is set, you should have the transfer happened and see the data in the destination buffer, you may need to do a cache invalidate to make sure CPU can see the data moved by EDMA.

    The ICRH bit needs to be set to clear the IPRH, either by ISR or polling. Polling should be simpler and you need clear the IPRH before the next EDMA transfer can happen. For the transfer, there is a field in the EDMA OPT: Transfer complete interrupt enable. or    Intermediate transfer completion interrupt enable. Try to change this to see if results changed. For the second interrupt no happening, do you see the data transfer at all?

    Regards, Eric

  • 0 in reply to lding
    Intellectual 540 points

    Hi,

    As I've supposed, the issue is on the CIC1 side. Once the transfer is completed, interrupt source must be acknowledge to allow next event trigger in edma:

    CpIntc_clearSysInt(1, 19);

    So now it' working as I want  and my data is availabled earlier.