Compiler/PROCESSOR-SDK-DRA7X: Use HDMI clock for LVDS output

Hello Brijesh

Please confirm Below Understanding.

 In DSS_CTRL (0x5800 0040)  Register. Bit Position:  9:7 ( F_CLK_SWITCH ) Below options are available and we have to choose option 0x3 for 

 Driving DSS with HDMI clock.  Please confirm my understanding 

0x0: DSS_CLK selected (from PRCM)
0x1: DPLL_DSI1_A_CLK1
0x2: DPLL_DSI1_B_CLK1
0x3: DPLL_HDMI_CLK1 selected (from DPLL_HDMI)
0x4: DPLL_DSI1_C_CLK1

Questions:

1. How can I do this change in the software, which file needs to be modified ? 

2. Do I update the Register direclty ?

Please confirm 

Regards,

Raghu

Hi Brijesh,

As per my understanding this API will change the clock for particular Vence ID. But the intent is that  complete DSS should be driven by HDMI clock not the individual LCD's.

Please correct if my understanding is wrong.

Thank you for you time,

Raghu

Hi Raghu,

Why do you want complete DSS to be driven by HDMI clock?

I guess you want LCD to be using HDMI clock source and outputting data at HDMI clock rate.. If this is true, then you just need to change clock source for that venc.. DSS will then also output at this clock rate..

Rgds,

Brijesh

Hi Brijesh,

please find below response in bold.

[Why do you want complete DSS to be driven by HDMI clock?]

This is one of the requirements to drive DSS from HDMI clock and as per my understanding the rational is that HDMI clock is stable compared to other clocks. 

[I guess you want LCD to be using HDMI clock source and outputting data at HDMI clock rate.. If this is true, then you just need to change clock source for that venc.. DSS will then also output at this clock rate..]

This is not our requirement

Regards,

Raghu

Hi Brijesh,

As per discussion internally please find below update.

[Why do you want complete DSS to be driven by HDMI clock?]

Raghu -  This is not  required

[I guess you want LCD to be using HDMI clock source and outputting data at HDMI clock rate.. If this is true, then you just need to change clock source for that venc.. DSS will then also output at this clock rate..]

Raghu - This is the requirment, will get back to you after analyzing the API which you have provided. 

Thank you ,

Raghu

Hi Brijesh,

We have an Early Camera scenario where in usecase is started from rtos.

Can I use API Bsp_platformSetVencClkSrc in the function   ChainsCommon_SetDctrlConfig() in below file 

vision_sdk/apps/src/rtos/usecases/common/chains_common.c. 

Bsp_PlatformVencSrc vencClkCfg;

vencClkCfg.vencClkSrc = BSP_PLATFORM_CLKSRC_DPLL_HDMI;
vencClkCfg.outputVenc = BSP_PLATFORM_VENC_LCD2 /* We are using LCD 2 */
Bsp_platformSetVencClkSrc(&vencClkCfg);

Please confirm above.

Regards,

Raghu

Hi Brijesh,

The concern here in is the following, after the clock source is set for the vencID(using below API)  just want to ensure that frame  work does'nt reset to default (may be because of some initialization is happening at the back end). So would like to know whether this is the correct place to set clock source. Any way will try this out and will keep you posted. 

Bsp_PlatformVencSrc vencClkCfg;

vencClkCfg.vencClkSrc = BSP_PLATFORM_CLKSRC_DPLL_HDMI;
vencClkCfg.outputVenc = BSP_PLATFORM_VENC_LCD2 /* We are using LCD 2 */
Bsp_platformSetVencClkSrc(&vencClkCfg);

Below is the usecase. 

Path: /home/workspace/3dot4/vision_sdk/apps/src/rtos/usecases/weston_dualcamera_dsswb

UseCase: weston_dualcamera_dsswb

Capture -> Display_Video
Capture_1 -> Display_Video1
DispDistSrc_gfx -> Display_gfx
DispDistSrc_vid3 -> Display_vid3
Capture_dsswb -> Alg_SwCrc

Regards,
Raghu

Hi Brijesh,

After making the changes, could'nt see any difference. Verification is done by checking below register values. 

DSS_CTRL: 0x5800 0040

root@mmt2020-a880:~# omapconf read 0x58000040
00011000

Bit 12: LCD2_CLK_SWITCH is  1 (0x1: DPLL_DSI1_B_CLK1 selected)

/* MUX CONTROL  for PLL */

CTRL_CORE_DSS_PLL_CONTROL

root@mmt2020-a880:~# omapconf read 0x4A002538
00000288

Bit: 6:5: DSI1_B_CLK1_SELECTION is 0 (0x0 = DPLL_VIDEO1).

Regards,
Raghu

Hi Brijesh,

To put it simply, there was no change in the register values after using the values which indicates the LCD2 Clock. 

If you need we can have webex session .

Note:

DSS_CTRL: 0x5800 0040 Indicates what Clock is selected for LCD2.

CTRL_CORE_DSS_PLL_CONTROL: PLL MUX confiugaration for LCD2. ( Here multiple options are availble, if clock is set to HDMI it will show in this register)

I think it is better to have short webex separately on this issue.

Regards,

Raghu

Hi Brijesh,

Please confirm whether we can have short meeting on Monday.

Regards,

Raghu 

Hi RAghu,

I discussed with Brijesh on this. He is suggesting if the settings can be done from PDK software and give a try if you can see the setting working as expected.

Can you please try this?

Thanks

RamPrasad

Hi Ram,

In PDK where and which file I have to add this change ?

Regards,

Raghu