AM5718: 8-bit NAND flash support

Hi,

Yes, 8-bit NAND is supported. See all requirements in section 33.3.7.4 of the AM571x TRM Rev. H. You must also ensure that SYSBOOT pins are configured correctly for NAND boot, and that the NAND is flashed with the correct ECC.

Hi, Biser Gatchev-XID

Thank you for your answer.

Thank you for your answer.

I am modifying by watching the dra72x evm code in u-boot.

But it doesn't work well. dra72x evm uses 16bit nand flash.

Are there any manuals that can tell me what needs to be modified to use 8bit?

Sunmin,

first, you need to see you get ROM to load SPL successfully. For this it'll important to configure the NAND size correctly using SYSBOOT pins as Biser suggested. Have you been able to move past this step?

From there on, the NAND configuration U-Boot uses is actually located in the arch/arm/include/asm/arch-omap5/mem.h header file, using the definitions below:

#define M_NAND_GPMC_CONFIG1	0x00000800
#define M_NAND_GPMC_CONFIG2	0x001e1e00
#define M_NAND_GPMC_CONFIG3	0x001e1e00
#define M_NAND_GPMC_CONFIG4	0x16051807
#define M_NAND_GPMC_CONFIG5	0x00151e1e
#define M_NAND_GPMC_CONFIG6	0x16000f80
#define M_NAND_GPMC_CONFIG7	0x00000008

For example, M_NAND_GPMC_CONFIG1 contains control bits that select the flash size (8-bit vs 16-bit) as per TRM register descriptions. You will need to update that list of constants to match your system.

Regards, Andreas

Hi, Andreas Dannenberg

M_NAND_GPMC_CONFIG1 is set to 8 bits.

However, when I do erase.part on u-boot and wirte, I get the following error message:

ECC is using BCH8.

Do I need to modify my ECC?

My NAND Flash has a byte4 of id 10h. Do you have to use bch16 in this case?

bch16 cannot be used due to size issues.

Is there any other way?

Hi Sunmin,

yes that looks like some configuration mismatch here. Give me a day or two to look into this a bit deeper.

Regards, Andreas

Hi Sunmin,

Sunmin Kim said:

M_NAND_GPMC_CONFIG1 is set to 8 bits.

I had another look, actually you should not need to update this baseline configuration for most cases. The most important settings are automatically tweaked based on this #define baseline in the omap_gpmc.c driver. For example, if you turn on CONFIG_SYS_NAND_BUSWIDTH_16BIT, the driver will update the GPMC configuration accordingly (this was just an example, for 8-bit bus operation like in your case CONFIG_SYS_NAND_BUSWIDTH_16BIT should NOT be set!)

I did some more looking, it turns out Phytec makes boards that use an 8-bit NAND devices (MT29F8G08ABACAWP) that seems similar to what you are using. It does use BCH16, not sure why you say this would be different for your chip? Anyways can you check/transplant their NAND U-Boot setup from the below link (I also captured the actual code below) to see if that works for you. If that's the case they have a wealth of other information too you can probably leverage pertaining to this NAND (such as Kernel dts setup, How-to guides, etc. - just look for "phyCORE-AM57x Linux BSP" and the associated source trees)

https://stash.phytec.com/projects/PUB/repos/uboot-phytec/browse/include/configs/am57xx_phycore_kit.h?at=refs%2Ftags%2FBSP-Yocto-TISDK-AM57xx-PD19.1.1#190

/* NAND support */

/* NAND: device related configs */
#define CONFIG_SYS_NAND_PAGE_SIZE	4096
#define CONFIG_SYS_NAND_OOBSIZE		224
#define CONFIG_SYS_NAND_BLOCK_SIZE	(64*4096)
#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
					 CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_5_ADDR_CYCLE

/* NAND: driver related configs */
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH16_CODE_HW
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
					 10, 11, 12, 13, 14, 15, 16, 17, \
					 18, 19, 20, 21, 22, 23, 24, 25, \
					 26, 27, 28, 29, 30, 31, 32, 33, \
					 34, 35, 36, 37, 38, 39, 40, 41, \
					 42, 43, 44, 45, 46, 47, 48, 49, \
					 50, 51, 52, 53, 54, 55, 56, 57, \
					 58, 59, 60, 61, 62, 63, 64, 65, \
					 66, 67, 68, 69, 70, 71, 72, 73, \
					 74, 75, 76, 77, 78, 79, 80, 81, \
					 82, 83, 84, 85, 86, 87, 88, 89, \
					 90, 91, 92, 93, 94, 95, 96, 97, \
					 98, 99, 100, 101, 102, 103, 104, \
					 110, 111, 112, 113, 114, 115, 116, \
					 117, 118, 119, 120, 121, 122, 123, \
					 124, 125, 126, 127, 128, 129, 130, \
					 131, 132, 133, 134, 135, 136, 137, \
					 138, 139, 140, 141, 142, 143, 144, \
					 145, 146, 147, 148, 149, 150, 151, \
					 152, 153, 154, 155, 156, 157, 158, \
					 159, 160, 161, 162, 163, 164, 165, \
					 166, 167, 168, 169, 170, 171, 172, \
					 173, 174, 175, 176, 177, 178, 179, \
					 180, 181, 182, 183, 184, 185, 186, \
					 187, 188, 189, 190, 191, 192, 193, \
					 194, 195, 196, 197, 198, 199, 200, \
					 201, 202, 203, 204, 205, 206, 207, \
					 208, 209,}

#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	26

#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x00100000

/* NAND: SPL falcon mode configs */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
#define CONFIG_CMD_SPL_WRITE_SIZE	0x2000
#endif

Regards, Andreas

Hi, Andreas Dannenberg

I have reviewed your example.

I want to know the difference in how to use bch16 and bch8.

In the case of phytec-am571x board, nand flash is used as below. The size calculation does not indicate a problem with the BCH16.

But when I use my nand flash bch16, there is a problem with the size and it prints out an error. So I use bch8 but I get an ecc error.

phytec bsp nand flash datasheet:

I suspect the following.

Other nand flash is reserved but my nand is defined as above. Can you find out if there are any changes that need to be made?

Hi, Andreas Dannenberg

After removing EEC Define, we could check the r / w operation. It seems to handle ecc part inside nand flash.

Can I boot SPL from NAND even if I use it this way?

Hi Sunmin,

Sunmin Kim said:

After removing EEC Define, we could check the r / w operation. It seems to handle ecc part inside nand flash.

Oh yes your device has built-in ECC, so you need to disable ECC in any user software such as U-Boot.

Sunmin Kim said:

Can I boot SPL from NAND even if I use it this way?

For this to work you need to disable ROM-based ECC checking via the SYSBOOT[9] signal by setting it to HIGH. Please also see this thread where a Flash device with on-chip ECC is used: https://e2e.ti.com/support/processors/f/791/t/867560  Configuring SYSBOOT[9] is what solved the basic boot issue there.

Regards, Andreas

Hi, Andreas Dannenberg

I succeeded in using nand flash in the bootloader but did not succeed in booting SPL from nand flash.

Can you explain the guide to booting MLO from NAND FLASH in am5718? I want to start looking for problems from the beginning. The SYSBOOT pin is [15: 0] = 1000000100111001.

Hi Sunmin,

looks like somebody had the exact same issue before, can you please review this response (and the associated thread in its entirety as needed)

https://e2e.ti.com/support/processors/f/791/p/538435/1966584#1966584

Please let me know what you encounter.

Regards, Andreas