OMAP-L138: Where should the program code reside for the code to run faster

Mahesh Godavarti

Part Number: OMAP-L138
Other Parts Discussed in Thread: OMAPL138

Hello, my code is taking way too long to execute. It is taking 34 seconds to process a 128ms frame.

Here is my linker command file (OMAPL138.cmd) that I obtained from code composer studio. Can you tell me which sections should be moved to IRAM for the code to run faster?

/****************************************************************************/
/* OMAPL138.cmd                                                            */
/* Copyright (c) 2010 Texas Instruments Incorporated                       */
/* Author: Rafael de Souza                                                 */
/*                                                                          */
/*    Description: This file is a sample linker command file that can be    */
/*                 used for linking programs built with the C compiler and */
/*                 running the resulting .out file on an OMAPL138           */
/*                 device. Use it as a guideline. You will want to        */
/*                 change the memory layout to match your specific          */
/*                 target system. You may want to change the allocation    */
/*                 scheme according to the size of your program.            */
/*                                                                          */
/*    Usage:       The map below contains the local memory for each core    */
/*                 Use the linker option --define=DSP_CORE=n                */
/*                 Where n defines the core used: DSP (n=1) or ARM (n=0)    */
/*                                                                          */
/****************************************************************************/

--args 0x0
-heap 0x40000
-stack 0x20000

MEMORY
{
#ifdef DSP_CORE /* DSP exclusive memory regions */

    DSPL2ROM     o = 0x00700000 l = 0x00100000 /* 1MB L2 DSP local ROM */
    DSPL2RAM     o = 0x00800000 l = 0x00040000 /* 256kB L2 DSP local RAM */
    DSPL1PRAM    o = 0x00E00000 l = 0x00008000 /* 32kB L1 DSP local Program RAM */
    DSPL1DRAM    o = 0x00F00000 l = 0x00008000 /* 32kB L1 DSP local Data RAM */

#endif

    SHDSPL2ROM   o = 0x11700000 l = 0x00100000 /* 1MB L2 Shared Internal ROM */
    SHDSPL2RAM   o = 0x11800000 l = 0x00040000 /* 256kB L2 Shared Internal RAM */
    SHDSPL1PRAM o = 0x11E00000 l = 0x00008000 /* 32kB L1 Shared Internal Program RAM */
    SHDSPL1DRAM o = 0x11F00000 l = 0x00008000 /* 32kB L1 Shared Internal Data RAM */
    EMIFACS0     o = 0x40000000 l = 0x20000000 /* 512MB SDRAM Data (CS0) */
    EMIFACS2     o = 0x60000000 l = 0x02000000 /* 32MB Async Data (CS2) */
    EMIFACS3     o = 0x62000000 l = 0x02000000 /* 32MB Async Data (CS3) */
    EMIFACS4     o = 0x64000000 l = 0x02000000 /* 32MB Async Data (CS4) */
    EMIFACS5     o = 0x66000000 l = 0x02000000 /* 32MB Async Data (CS5) */
    SHRAM        o = 0x80000000 l = 0x00020000 /* 128kB Shared RAM */
    DDR2         o = 0xC0000000 l = 0x20000000 /* 512MB DDR2 Data */

#ifndef DSP_CORE /* ARM exclusive memory regions */

ARMROM o = 0xFFFD0000 l = 0x00010000 /* 64kB ARM local ROM */
ARMRAM o = 0xFFFF0000 l = 0x00002000 /* 8kB ARM local RAM */

#endif
}

SECTIONS
{
    .text          > DDR2
    .stack         > DDR2
    .bss           > DSPL2RAM
    .heap          > DSPL2RAM
    .cio           > DDR2
    .const         > DDR2
    .data          > DSPL2RAM
    .switch        > DDR2
    .sysmem        > DSPL2RAM
    .far           > DDR2
    .args          > DDR2
    .ppinfo        > DDR2
    .ppdata        > DDR2

    /* TI-ABI or COFF sections */
    .pinit         > DDR2
    .cinit         > DDR2

    /* EABI sections */
    .binit         > DDR2
    .init_array    > DDR2
    .neardata      > DDR2
    .fardata       > DDR2
    .rodata        > DDR2
    .c6xabi.exidx > DDR2
    .c6xabi.extab > DDR2
}

over 5 years ago

0 Sahin Okur over 5 years ago

TI__Mastermind 27355 points

Hello,

Generally speaking, whatever your application uses the most should be placed in internal memory for the best performance. If you have any buffers that are constantly being accessed they should be placed in IRAM. You can refer to your map file to see what's inside each section.

You can also try setting L2 as cache and enabling cache if you haven't tried that already.

Turning on compiler optimization for speed is another option as well.

I'm adding some useful links below.

TMS320C6000 Assembly Language Tools v8.2.x User's Guide (Rev. B)

C6000 Embedded Design Workshop - C6000 Optimizations

TMS320C6000 Optimizing Compiler v8.3.x

Regards,
Sahin

0 Mahesh Godavarti over 5 years ago in reply to Sahin Okur

Intellectual 630 points

Hi Sahin, can you point me to a tutorial that walks me through setting up cache on L2?

Thanks!

0 Sahin Okur over 5 years ago in reply to Mahesh Godavarti

TI__Mastermind 27355 points

I could not find a tutorial so I will try to explain. Let me know if you run into issues or have questions.

On the DSP, the L2 has a set of registers for configuring the cache, known as Memory Attribute Registers (MAR). You will need to set the appropriate MAR register to enable cache for a given region.

Refer to Table 4-21 in TMS320C674x DSP Megamodule Reference Guide for the register <-> region mapping.

For example, to set the region 0xc4000000 -> 0xc4ffffff to be cached you would add the following to your .cfg file.

var Cache = xdc.useModule('ti.sysbios.family.c64p.Cache');

Cache.MAR192_223 = 0x00000010;

You can then check ROV in CCS after your code has run to verify the region is cached as expected.

For your reference:

https://training.ti.com/c6000-cache-overview-7-15

TMS320C674x DSP Cache User's Guide

Regards,
Sahin

0 Mahesh Godavarti over 5 years ago in reply to Sahin Okur

Intellectual 630 points

Thanks very much Sahin.

Three questions:

1. How do I add a .cfg file to my project?

2. Is there a way to do this without using a .cfg file? E.g. similar to the approach presented in the user guide? What libraries should I download for this? Are these libraries available in COFF format?

3. What is ROV?

0 Mahesh Godavarti over 5 years ago in reply to Mahesh Godavarti

Intellectual 630 points

Sahin, I figure out how to add a .cfg file.

I did "right-click -> New -> Other -> RTSC Configuration file"

Is this correct?

0 Mahesh Godavarti over 5 years ago in reply to Mahesh Godavarti

Intellectual 630 points

Hi Sahin, can you please let me know how to enable cache without using .cfg file?

I was successful doing it, but I was forced to switch to ELF format. I want to be able to do this in COFF format.

I tried following TMS320C74x DSP Cache User's Guide, but I have not been able to find the library that goes with this user guide. Can you please point me in the right direction? Does this library come in COFF format?

0 Mahesh Godavarti over 5 years ago in reply to Mahesh Godavarti

Intellectual 630 points

Hi Sahin, can you also show me how to enable both L1 and L2 Cache using the .cfg file?

Essentially, I have two questions:

1. How can I enable L1 and L2 Cache using the .cfg file (using compiler v8.3.5)

2. How can I enable L2 and L2 Cache without using the .cfg file for a COFF executable (using compiler v7.4.13)

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OMAP-L138: Where should the program code reside for the code to run faster