Hi,
I need to use the AARCH32 execution mode for Cortex-A53. I have modified the SBL source like below (RED color indicates modifications) and able to switch the execution mode from default AARCH64 to required AARCH32.
File: sbl_slave_core_boot.c
Function: SBL_SlaveCoreBoot()
---
proc_set_config_req.processor_id = sblSlaveCoreInfoPtr->tisci_proc_id;
proc_set_config_req.bootvector_lo = pAppEntry->CpuEntryPoint[core_id];
proc_set_config_req.bootvector_hi = 0x0;
proc_set_config_req.config_flags_1_set = 0;
proc_set_config_req.config_flags_1_clear = 0;
/* For Cortex-A53 CPUs, set the execution mode to AARCH32 */
if ( (core_id == MPU1_CPU0_ID) || (core_id == MPU1_CPU1_ID) || (core_id == MPU2_CPU0_ID) || (core_id == MPU1_CPU1_ID) )
{
proc_set_config_req.config_flags_1_set |= TISCI_MSG_VAL_PROC_BOOT_CFG_FLAG_ARMV8_AARCH32;
}
if (pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR) /* Set entry point only is valid */
---
My questions are:
Q1) Do I need to consider any other modification to boot the Cortex-A53 cores in AARCH32 mode?
Q2) Is there any example app (like k3MulticoreApp) for AARCH32 mode instead of AARCH64?
Q3) After connecting to the Cortex-A53_cluster0_core0 via JTAG, I am not being able to set the GIC's ICC_SRE to enable access to the CPU interface of GIC. I have used the following code in my reset vector e.g.
---
mov r0, #7
mcr p15, 0, r0, c12, c12, 5 /* Write r0 to ICC_SRE */
---
The above statements are not being able to set concerned bits in ICC_SRE. Any idea? Any help is highly appreciated.
Regards,
Hasan
