TDA4VMXEVM: TDA4 interrupt lists

Hi Michael,

Are you looking for something like this -

Regards,

Karan

hi,

 Ipc_MbConfig:

    Could you provide the mapping table between  inputIntrNum / outputIntrNum / eventID about mailbox in PSDKRA/PDK/drv/IPC.

    Especially outputIntrNum, I really can't find the corresponding relationship from 《technical reference manual》.

Regards

hi,  Karan

Refer to《j721 DRA829/TDA4VM/AM752x Processors Silicon Revision 1.0  Technical Reference Manual  》：

  9.1 Interrupt Architecture：

Can you show me the interrupt architecture of tda4? I'm really confused about the interrupt architecture.

Regards

Hi Michael,

https://lwn.net/Articles/775615/

This has some more explanation of high level interrupt architecture of k3 family based SoCs(Including tda4). 

INTA - Interrupt aggregator described in depth: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.txt

INTR - Interrupt router described in depth: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt

Is that something you are looking for?

Best Regards,
Keerthy

Hi Michael,

What you need is - http://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721e/irq_sources.html

and http://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721e/irq_dsts.html

These provide the mapping for interrupt sources to Interrupt routers and interrupt destinations for Interrupt routers. That is the information you need to map the interrupts from peripherals to CPUs. Using these parameters you can call the Sciclient APIs to configure the interrupt routers.

Regards,

Karan

Hi Michael,

You can use it like the following (psdk_rtos_auto_j7_06_02_00_21/mcusw/mcal_drv/mcal/examples/Can/soc/j721e/mcu1_0/CanApp_Startup.c)

454         {                                                                       
455             CanApp_IntNumbers[idx]          = CanApp_RoutIntNumbers[idx];       
456             rmIrqReq.valid_params           = TISCI_MSG_VALUE_RM_DST_ID_VALID;  
457             rmIrqReq.valid_params          |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
458             rmIrqReq.src_id                 = CanApp_InstanceSrcId[idx];        
459             rmIrqReq.global_event           = 0U;                               
460             /* Src Index 0 - mcanss_ext_ts_rollover_lvl_int,                    
461                Src Index 1 - mcanss_mcan_lvl_int Line 0,                        
462                Src Index 2 - mcanss_mcan_lvl_int Line 1 */                      
463             rmIrqReq.src_index              = 1U;                               
464             rmIrqReq.dst_id                 = TISCI_DEV_MCU_R5FSS0_CORE0;       
465             rmIrqReq.dst_host_irq           = CanApp_RoutIntNumbers[idx];       
466             rmIrqReq.ia_id                  = 0U;                               
467             rmIrqReq.vint                   = 0U;                               
468             rmIrqReq.vint_status_bit_index  = 0U;                               
469             rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
470             retVal = Sciclient_rmIrqSet(                                        
471                          &rmIrqReq, &rmIrqResp, APP_SCICLIENT_TIMEOUT);         
472             if(CSL_PASS != retVal)                                              
473             {                                                                   
474                 AppUtils_Printf(MSG_NORMAL,                                     
475                 "CAN_APP: Error in SciClient Interrupt Params Configuration!!!\n");
476             }                                                                   
477         }                                                                       
478                                                                                 

Regards,

Karan

>>>The outputs of Interrupt routers are hard-wired to the CORE's interrupts. So this configuration is hard wired, that is what the table denotes. Now from this >>>information we see that R5FSS0_CORE0's interrupt number 248 is connected to NAVSS0_INTR_ROUTER_0's 216th output line.

>>>Now we can route any interrupt coming on the inputs to NAVSS0_INTR_ROUTER_0 and route it to NAVSS0_INTR_ROUTER_0's 216 output and in turn >>>this will interrupt the R5FSS0_CORE0 by generating an interrupt on its 248 interrupt.

Do you have any documents about 248? I can't find it from the link above.

Regards

Thanks , About R5F this resolved my issue.

but i have som issue about C66_0/C66_1/C71.

In source code psdk_rtos_auto_j7_06_02_00_21/pdk/packages/ti/drv/ipc/soc/V1/ipc_soc.h

#define NAVSS512_C66X1_INPUT_MAILBOX_OFFSET  344U /* C66x_interRoute_0 : 96 */

#define NAVSS512_C66X2_INPUT_MAILBOX_OFFSET  376U /* C66x_interRoute_1 : 96 */

#define NAVSS512_C7X1_INPUT_MAILBOX_OFFSET  188U

But, C66_0:

C66_1:

C71:

For C66, the code is 96, but the document is 97. Who is right?

For C71 , the code is 51, but the document is 732. Who is right?

Regards

Hi Michael,

The delta might be because the link you are referring to is the latest TISCI (this has come with the SDK 7.0 release) and you are using the old one (with SDK 6.02). Whatever is there is the code can be assumed correct, I can look at the public link for the old TISCI and send you that.

Are you facing some issue regarding this or was it just to confirm? Because the code should take care this.

Regards,

Karan