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AM5716: ECC function for DDR

Hitoshi Sugawara
Mastermind 20450 points

Part Number: AM5716

Hi Experts,

Le me clarify a couple of questions for ECC for DDR.

1) According to the TRM www.ti.com/lit/SPRUHZ7, it says "The ECC feature is not available on this device," in 15.3.4.14.
However, the errata http://www.ti.com/lit/SPRZ436 describes the limitation of the ECC function ( Workaround ).
Does this mean the ECC function in AM571x is workable if the workaround is followed?

2) If ECC function is not guaranteed, are there any ways to detect error and correct it without changing CPU?

3) For the errata i922.
When the memory initialization just after ECC enabled, zero must be written with 32bit DDR width.
Is it possible if 16 bit access from IPU, USB, or eMMC through DMA transfer is done.
Or does every write access have to be aligned with 32 bit width for all area where ECC enabled?

Thank you in advance for your kind clarification.
Best regards,
Hitoshi

 

  • 0
    TI__Mastermind 41240 points

    Hi,

    For #1, i922 greatly limits the usability of ECC, as all accesses must be quanta sized and aligned. As mentioned in the work-around, TI does not support making these modifications. 

    For #2, I am not aware of other hardware features to detect / correct errors on AM571x. 

    For #3, my understanding is that the ECC memory region needs to be primed (written to) before accessing via reads. I am not aware of any specific data value that must be written. Accesses must be quanta sized and aligned for the entire memory region where ECC is enabled.

    Best regards,
    Kevin

  • 0 in reply to Kevin S
    TI__Mastermind 20450 points

    Hi Kevin,

    Thank you so much for your quick reply.
    I have dispatched the answer to the customer.
    If there is further questions, will continue the thread.

    Best regards,
    Hitoshi