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Tool/software: TI C/C++ Compiler
Hi,
I want to load mcspi_slavemode APP from eMMC.
What should I do?
Is there any guideline can provide?
Best Regard,
Leo Ho
Hi Karan,
I'm on the latest SDK 6.02.
Yes, I want to use SBL to run the app, the app will just run on MCU UART from eMMC.
Thank you.
Best Regard,
Leo Ho
Hi Leo Ho,
There is some limitation in running mcspi_slaveapp using the SBL. Can you please look at - https://e2e.ti.com/support/processors/f/791/t/902713
Regards,
Karan
Hi Karan,
I know have some limitation, and we need to use SBL run the app from eMMC.
Thanks again.
Best Regard,
Leo Ho
Hi Karan,
I have try the method to load app from eMMC, there is the process below:
MCSPI_MasterSlave_j721e_evm_mcu1_0TestApp_release.xer5f rename to j7-mcu-r5f0_0-fw
=> load mmc 0:1 0x89000000 /lib/firmware/j7-mcu-r5f0_0-fw
2725696 bytes read in 11 ms (236.3 MiB/s)
=> rproc init
=> rproc load 0 0x89000000 0x${filesize}
Load Remote Processor 0 with data@addr=0x89000000 2725696 bytes: Success!
=> rproc start 0
But there is no log in any UART.
What problem with it, and how to solve it?
Best Regard,
Leo Ho
Hi Leo,
leo ho said:I have try the method to load app from eMMC, there is the process below:
MCSPI_MasterSlave_j721e_evm_mcu1_0TestApp_release.xer5f rename to j7-mcu-r5f0_0-fw
The way you are trying to load the app is using u-boot. I recollect you mentioning that you want to use SBL.
leo ho said:But there is no log in any UART.
What problem with it, and how to solve it?
So if you look at the documentation of the application, \details in the comments in main_mcspi_slave_mode.c
Master app runs on mcu1_0 and slave app runs on mpu1_0.
23 * For AM65xx and J721e devices, to demonstrate the example two cores 24 * on the same SoC are needed, mcu1_0 uses McSPI instance 2 on the MCU 25 * domain as the master and mpu1_0 uses McSPI instance 4 on the Main 26 * doman as slave. These two instances are internally connected in the SoC: 27 * 28 * Following is the internal pin signal connection information: 29 * MasterSPI_SCLK----SlaveSPI_SCLK 30 * MasterSPI_D1------SlaveSPI_D0 31 * MasterSPI_D0------SlaveSPI_D1 32 * MasterSPI_CS------SlaveSPI_CS 33 * 34 * To run the example: 35 * 1) Run the MasterSlave mpu1_0 test binary (slave) on MPU1_0 core 36 * 2) Run the MasterSlave mcu1_0 test binary (master) on MCU1_0 core 37 * 3) Be sure to run slave application and then master application
So you need to load both the Master and the Slave app and then run the slave first fore the master.
If you look at https://e2e.ti.com/support/processors/f/791/p/902713/3344543#3344543 then it shows how you can combine the Master and slave apps and then load using SBL. So when you load only the master (MCU1_0 application) then it is bound to not print anything. When you are running linux along with this then you can not load the Slave binary on MPU1_0 (A72) as it is running linux.
So I would suggest if you are trying to use the MCSPI application, you use CCS to validate it. (this is the supported method)
Regards,
Karan
Hi Karan,
Sorry for my incorrect reply, I need to run single app (MCSPI_MasterSlave_j721e_evm_mcu1_0TestApp_release.xer5f on MCU1_0) from u-boot.
Because of our custom board, we can't use CCS tool to validate the application.
We only run MCSPI slave app on MCU1_0 for communicatie with external device (as master).
I have try the method from this thread https://e2e.ti.com/support/processors/f/791/p/922411/3419862?tisearch=e2e-sitesearch&keymatch=loading%252525252520MCU1_0%252525252520with%252525252520R5%252525252520emmc#pi320966=1, but there have some problem over here https://e2e.ti.com/support/processors/f/791/t/930278 .
Can you help me about this thread?
Thanks a lot.
Best Regard,
Leo Ho
Hi Leo,
There could be an issue with the communication too rather than the loading. Can you try adding some initial prints to the application, just inside main() and then see if those are getting printed? Reason I ask this is because in I tried to run the mcu1_0 application only and it doesn't print anything if the slave app is not there.
But just to note, we haven't validated this application with u-boot.
Regards,
Karan
Hi Karan,
I add log in main(), but still no any log printed out.
I use auto load from u-boot, it has load success.
Load Remote Processor 0 with data@addr=0x80080000 2728212 bytes: Success!
Has other way need to try or need to provide any information for you?
Thanks for your quick reply!
Best Regard,
Leo Ho
Hi Leo ho,
Can you share the linker command file and the generated map file?
There are some thing to take care of like Reset vectors should be in ATCM and you should not have MPU and Cache configuration code in DDR. These things are mentioned in https://e2e.ti.com/support/processors/f/791/t/915474
Regards,
Karan
Hi Karan,
These is the linker file and the generated map file.
/* linker options */
--fill_value=0
--stack_size=0x2000
--heap_size=0x1000
-e __VECS_ENTRY_POINT
MEMORY
{
R5F_TCMA_SBL_RSVD(X) : ORIGIN = 0x00000000 , LENGTH = 0x100
MCU0_R5F_TCMA (X) : origin = 0x100 , length = 0x8000 - 0x100
RESET_VECTORS(X) : ORIGIN = 0x41c40000 , LENGTH = 0x100 /* Bottom 256 KB used by SBL */
R5F_TCMB0(RWIX) : ORIGIN = 0x41010000 , LENGTH = 0x00008000
MSMC3(RWIX) : ORIGIN = 0x70080000 , LENGTH = 0x770000
DDR0(RWIX) : ORIGIN = 0x80000000 , LENGTH = 0x80000000
MCU1_0_MSRAM : origin = 0x41C40100 , length = 0x5C000 - 0x100
}
SECTIONS
{
.vecs : {
__VECS_ENTRY_POINT = .;
} palign(8) > R5F_TCMA_SBL_RSVD
.text_boot {
*boot.aer5f<*boot.o*>(.text)
} palign(8) > MCU0_R5F_TCMA
.text:xdc_runtime_Startup_reset__I : {} palign(8) > MCU0_R5F_TCMA
.text:ti_sysbios_family_arm_v7r_Cache* : {} palign(8) > MCU0_R5F_TCMA
.text:ti_sysbios_family_arm_MPU* : {} palign(8) > MCU0_R5F_TCMA
.rstvectors : {} palign(8) > MCU1_0_MSRAM
/* For NDK packet memory, we need to map this sectionsbefore .bss*/
.bss:NDK_MMBUFFER (NOLOAD) {} ALIGN (128) > MCU1_0_MSRAM
.bss:NDK_PACKETMEM (NOLOAD) {} ALIGN (128) > MCU1_0_MSRAM
.intvecs : {} palign(8) > MCU1_0_MSRAM
.bss : {} align(4) > MCU1_0_MSRAM
.text : {} palign(8) > MCU1_0_MSRAM
.cinit : {} palign(8) > MCU1_0_MSRAM
.bss : {} align(8) > MCU1_0_MSRAM
.far : {} align(8) > MCU1_0_MSRAM
.const : {} palign(8) > MCU1_0_MSRAM
.data : {} palign(128) > MCU1_0_MSRAM
.sysmem : {} align(8) > MCU1_0_MSRAM
.stack : {} align(4) > MCU1_0_MSRAM
.data_buffer: {} palign(128) > MCU1_0_MSRAM
}
When I auto load the app from u-boot and boot.
When boot in kernel, it stuck in ti-sci in our custom board.
U-Boot SPL 2019.01-g753252f622-dirty (Aug 06 2020 - 06:45:51 +0000) SYSFW ABI: 2.9 (firmware rev 0x0013 '19.12.1-v2019.12a (Terrific Lla') Reading on-board EEPROM at 0x50 failed 1 Trying to boot from SPI Loading Environment from MMC... spl: unsupported mmc boot device. sdhci@4f80000 - probe failed: -19 *** Warning - No MMC card found, using default environment Loading rproc fw image from device 3 not supported! Loading rproc fw image from device 3 not supported! Starting ATF on ARM64 core... NOTICE: BL31: v2.2(release):ti2019.05-rc1 NOTICE: BL31: Built : 03:48:29, Jun 18 2020 I/TC: I/TC: OP-TEE version: ti2019.05-rc1-dev (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #1 Thu Jun 18 03:53:19 UTC 2020 aarch64 I/TC: Initialized U-Boot SPL 2019.01-g753252f622-dirty (Aug 06 2020 - 07:03:57 +0000) Reading on-board EEPROM at 0x50 failed 1 Trying to boot from SPI U-Boot 2019.01-g753252f622-dirty (Aug 06 2020 - 07:03:57 +0000) SoC: J721E PG 1.0 Model: Texas Instruments K3 J721E SoC Reading on-board EEPROM at 0x50 failed 1 Board: J721EX-PM1-SOM rev E2 DRAM: 4 GiB Flash: 0 Bytes MMC: sdhci@4f80000: 0 Loading Environment from MMC... OK In: serial@2800000 Out: serial@2800000 Err: serial@2800000 Reading on-board EEPROM at 0x50 failed 1 Net: Sentinen Print pull high reset eth0: ethernet@046000000 Hit any key to stop autoboot: 0 switch to partitions #0, OK mmc0(part 0) is current device SD/MMC found on device 0 ** File not found boot.scr ** ** Unrecognized filesystem type ** 2726224 bytes read in 12 ms (216.7 MiB/s) Load Remote Processor 0 with data@addr=0x80080000 2726224 bytes: Success! ** File not found /lib/firmware/j7-main-r5f0_1-fw ** ** File not found /lib/firmware/j7-main-r5f1_0-fw ** ** File not found /lib/firmware/j7-c66_0-fw ** ** File not found /lib/firmware/j7-c66_1-fw ** ** File not found /lib/firmware/j7-c71_0-fw ** 17303560 bytes read in 58 ms (284.5 MiB/s) 100148 bytes read in 1 ms (95.5 MiB/s) ## Flattened Device Tree blob at 82000000 Booting using the fdt blob at 0x82000000 Loading Device Tree to 00000000fdda3000, end 00000000fdebefff ... OK Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080] [ 0.000000] Linux version 4.19.94-gf5fb92aa92 (oe-user@oe-host) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #1 SMP PREEMPT Tue Aug 11 00:38:43 UTC 2020 [ 0.000000] Machine model: Texas Instruments K3 J721E SoC [ 0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002800000 (options '') [ 0.000000] bootconsole [ns16550a0] enabled [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB [ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a0000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB [ 0.000000] OF: reserved mem: initialized node r5f-memory@a0100000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB [ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a1000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a1100000, size 15 MiB [ 0.000000] OF: reserved mem: initialized node r5f-memory@a1100000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 1 MiB [ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a2000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a2100000, size 15 MiB [ 0.000000] OF: reserved mem: initialized node r5f-memory@a2100000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a3000000, size 1 MiB [ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a3000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a3100000, size 15 MiB [ 0.000000] OF: reserved mem: initialized node r5f-memory@a3100000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a4000000, size 1 MiB [ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a4000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a4100000, size 15 MiB [ 0.000000] OF: reserved mem: initialized node r5f-memory@a4100000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a5000000, size 1 MiB [ 0.000000] OF: reserved mem: initialized node r5f-dma-memory@a5000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a5100000, size 15 MiB [ 0.000000] OF: reserved mem: initialized node r5f-memory@a5100000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a6000000, size 1 MiB [ 0.000000] OF: reserved mem: initialized node c66-dma-memory@a6000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a6100000, size 15 MiB [ 0.000000] OF: reserved mem: initialized node c66-memory@a6100000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a7000000, size 1 MiB [ 0.000000] OF: reserved mem: initialized node c66-dma-memory@a7000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a7100000, size 15 MiB [ 0.000000] OF: reserved mem: initialized node c66-memory@a7100000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a8000000, size 1 MiB [ 0.000000] OF: reserved mem: initialized node c71-dma-memory@a8000000, compatible id shared-dma-pool [ 0.000000] Reserved memory: created DMA memory pool at 0x00000000a8100000, size 15 MiB [ 0.000000] OF: reserved mem: initialized node c71-memory@a8100000, compatible id shared-dma-pool [ 0.000000] cma: Reserved 512 MiB at 0x00000000c0000000 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.1 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: Trusted OS migration not required [ 0.000000] psci: SMC Calling Convention v1.1 [ 0.000000] random: get_random_bytes called from start_kernel+0x94/0x3e4 with crng_init=0 [ 0.000000] percpu: Embedded 2 pages/cpu s48536 r8192 d74344 u131072 [ 0.000000] Detected PIPT I-cache on CPU0 [ 0.000000] CPU features: enabling workaround for EL2 vector hardening [ 0.000000] Speculative Store Bypass Disable mitigation not required [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 62339 [ 0.000000] Kernel command line: console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000 mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs) root=PARTUUID=a3179f72-7984-407e-bdf3-c374e0d3d24f rw rootfstype=ext4 rootwait [ 0.000000] Dentry cache hash table entries: 524288 (order: 6, 4194304 bytes) [ 0.000000] Inode-cache hash table entries: 262144 (order: 5, 2097152 bytes) [ 0.000000] software IO TLB: mapped [mem 0xf9da0000-0xfdda0000] (64MB) [ 0.000000] Memory: 3373696K/3993600K available (10814K kernel code, 1410K rwdata, 3968K rodata, 640K init, 718K bss, 95616K reserved, 524288K cma-reserved) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 [ 0.000000] rcu: Preemptible hierarchical RCU implementation. [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=2. [ 0.000000] Tasks RCU enabled. [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 [ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode [ 0.000000] GICv3: Distributor has no Range Selector support [ 0.000000] GICv3: no VLPI support, no direct LPI support [ 0.000000] ITS [mem 0x01820000-0x0182ffff] [ 0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS [ 0.000000] ITS@0x0000000001820000: allocated 1048576 Devices @8c0800000 (flat, esz 8, psz 64K, shr 0) [ 0.000000] ITS: using cache flushing for cmd queue [ 0.000000] GIC: using LPI property table @0x00000008c00a0000 [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000 [ 0.000000] CPU0: using LPI pending table @0x00000008c00b0000 [ 0.000000] GIC: using cache flushing for LPI property table [ 0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys). [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns [ 0.000002] sched_clock: 56 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns [ 0.008374] Console: colour dummy device 80x25 [ 0.012928] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000) [ 0.023596] pid_max: default: 32768 minimum: 301 [ 0.028334] Security Framework initialized [ 0.032538] Mount-cache hash table entries: 8192 (order: 0, 65536 bytes) [ 0.039393] Mountpoint-cache hash table entries: 8192 (order: 0, 65536 bytes) [ 0.070727] ASID allocator initialised with 32768 entries [ 0.084252] rcu: Hierarchical SRCU implementation. [ 0.097196] Platform MSI: gic-its@1820000 domain created [ 0.102732] PCI/MSI: /interconnect@100000/interrupt-controller@1800000/gic-its@1820000 domain created [ 0.120167] smp: Bringing up secondary CPUs ... [ 0.157066] Detected PIPT I-cache on CPU1 [ 0.157082] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000 [ 0.157111] CPU1: using LPI pending table @0x00000008c0310000 [ 0.157133] CPU1: Booted secondary processor 0x0000000001 [0x411fd080] [ 0.157172] smp: Brought up 1 node, 2 CPUs [ 0.185009] SMP: Total of 2 processors activated. [ 0.189819] CPU features: detected: GIC system register CPU interface [ 0.196401] CPU features: detected: 32-bit EL0 Support [ 0.201883] CPU: All CPU(s) started at EL2 [ 0.206070] alternatives: patching kernel code [ 0.211055] devtmpfs: initialized [ 0.218805] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns [ 0.228768] futex hash table entries: 512 (order: -1, 32768 bytes) [ 0.235469] pinctrl core: initialized pinctrl subsystem [ 0.241139] NET: Registered protocol family 16 [ 0.246047] vdso: 2 pages (1 code @ (____ptrval____), 1 data @ (____ptrval____)) [ 0.253610] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers. [ 0.262798] DMA: preallocated 256 KiB pool for atomic allocations [ 0.283522] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages [ 0.290375] HugeTLB registered 512 MiB page size, pre-allocated 0 pages [ 0.297780] cryptd: max_cpu_qlen set to 1000 [ 0.302636] vsys_3v3: supplied by evm_12v0 [ 0.306899] vsys_5v0: supplied by evm_12v0 [ 0.311407] SCSI subsystem initialized [ 0.315291] usbcore: registered new interface driver usbfs [ 0.320906] usbcore: registered new interface driver hub [ 0.326353] usbcore: registered new device driver usb [ 0.331707] media: Linux media interface: v0.10 [ 0.336342] videodev: Linux video capture interface: v2.00 [ 0.341955] pps_core: LinuxPPS API ver. 1 registered [ 0.347024] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> [ 0.356360] PTP clock support registered [ 0.360371] EDAC MC: Ver: 3.0.0 [ 0.364199] Advanced Linux Sound Architecture Driver Initialized. [ 0.370592] Bluetooth: Core ver 2.22 [ 0.374249] NET: Registered protocol family 31 [ 0.378789] Bluetooth: HCI device and connection manager initialized [ 0.385281] Bluetooth: HCI socket layer initialized [ 0.390262] Bluetooth: L2CAP socket layer initialized [ 0.395430] Bluetooth: SCO socket layer initialized [ 0.400627] clocksource: Switched to clocksource arch_sys_counter [ 0.406906] VFS: Disk quotas dquot_6.6.0 [ 0.410950] VFS: Dquot-cache hash table entries: 8192 (order 0, 65536 bytes) [ 0.420298] NET: Registered protocol family 2 [ 0.425038] tcp_listen_portaddr_hash hash table entries: 4096 (order: 0, 65536 bytes) [ 0.433106] TCP established hash table entries: 32768 (order: 2, 262144 bytes) [ 0.440591] TCP bind hash table entries: 32768 (order: 3, 524288 bytes) [ 0.447596] TCP: Hash tables configured (established 32768 bind 32768) [ 0.454336] UDP hash table entries: 2048 (order: 0, 65536 bytes) [ 0.460518] UDP-Lite hash table entries: 2048 (order: 0, 65536 bytes) [ 0.467187] NET: Registered protocol family 1 [ 0.471861] RPC: Registered named UNIX socket transport module. [ 0.477914] RPC: Registered udp transport module. [ 0.482717] RPC: Registered tcp transport module. [ 0.487520] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 0.494564] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available [ 0.504164] Initialise system trusted keyrings [ 0.508773] workingset: timestamp_bits=46 max_order=16 bucket_order=0 [ 0.516760] squashfs: version 4.0 (2009/01/31) Phillip Lougher [ 0.522908] NFS: Registering the id_resolver key type [ 0.528078] Key type id_resolver registered [ 0.532350] Key type id_legacy registered [ 0.536448] nfs4filelayout_init: NFSv4 File Layout Driver Registering... [ 0.543351] 9p: Installing v9fs 9p2000 file system support [ 0.550481] Key type asymmetric registered [ 0.554668] Asymmetric key parser 'x509' registered [ 0.559668] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245) [ 0.567228] io scheduler noop registered [ 0.571233] io scheduler deadline registered [ 0.575633] io scheduler cfq registered (default) [ 0.580439] io scheduler mq-deadline registered [ 0.585065] io scheduler kyber registered [ 0.589953] pinctrl-single 4301c000.pinmux: 94 pins, size 376 [ 0.596031] pinctrl-single 11c000.pinmux: 173 pins, size 692 [ 0.602143] pinctrl-single a40000.timesync_router: 512 pins, size 2048 [ 0.611085] ti-pat 31010000.pat: Found PAT Rev 1.0 with 16384 pages [ 0.617508] ti-pat 31010000.pat: Failed to create 31010000.pat debugfs directory [ 0.625193] ti-pat 31011000.pat: Found PAT Rev 1.0 with 16384 pages [ 0.631606] ti-pat 31011000.pat: Failed to create 31011000.pat debugfs directory [ 0.639266] ti-pat 31012000.pat: Found PAT Rev 1.0 with 16384 pages [ 0.645678] ti-pat 31012000.pat: Failed to create 31012000.pat debugfs directory [ 0.653361] ti-pat 31013000.pat: Found PAT Rev 1.0 with 2048 pages [ 0.659685] ti-pat 31013000.pat: Failed to create 31013000.pat debugfs directory [ 0.667332] ti-pat 31014000.pat: Found PAT Rev 1.0 with 2048 pages [ 0.673655] ti-pat 31014000.pat: Failed to create 31014000.pat debugfs directory [ 0.682604] Serial: 8250/16550 driver, 10 ports, IRQ sharing enabled [ 0.693831] brd: module loaded [ 0.699576] loop: module loaded [ 0.703882] libphy: Fixed MDIO Bus: probed [ 0.708234] tun: Universal TUN/TAP device driver, 1.6 [ 0.713634] igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.4.0-k [ 0.721643] igbvf: Copyright (c) 2009 - 2012 Intel Corporation. [ 0.727707] sky2: driver version 1.30 [ 0.731976] RTW: module init start [ 0.735455] RTW: rtl88x2ce v5.7.3_35403.20191028 [ 0.740170] RTW: build time: Aug 11 2020 00:46:26 [ 0.744975] RTW: rtl88x2ce BT-Coex version = COEX20190318-00 [ 0.750766] RTW: rtw_inetaddr_notifier_register [ 0.755404] RTW: module init ret=0 [ 0.758888] usbcore: registered new interface driver asix [ 0.764420] usbcore: registered new interface driver ax88179_178a [ 0.770654] usbcore: registered new interface driver cdc_ether [ 0.776625] usbcore: registered new interface driver net1080 [ 0.782417] usbcore: registered new interface driver cdc_subset [ 0.788472] usbcore: registered new interface driver zaurus [ 0.794177] usbcore: registered new interface driver cdc_ncm [ 0.799966] usbcore: registered new interface driver qmi_wwan [ 0.805846] usbcore: registered new interface driver qmi_wwan_q [ 0.811901] usbcore: registered new interface driver cdc_mbim [ 0.817822] VFIO - User Level meta-driver version: 0.3 [ 0.823317] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver [ 0.829641] ohci-pci: OHCI PCI platform driver [ 0.834190] ohci-platform: OHCI generic platform driver [ 0.839625] usbcore: registered new interface driver cdc_wdm [ 0.845421] usbcore: registered new interface driver usb-storage [ 0.851584] usbcore: registered new interface driver option [ 0.857284] usbserial: USB Serial support registered for GSM modem (1-port) [ 0.864693] i2c /dev entries driver [ 0.868520] rtk_btusb: Realtek Bluetooth USB driver ver 3.1 [ 0.874214] rtk_btcoex: rtk_btcoex_init: version: 1.2 [ 0.879372] rtk_btcoex: create workqueue [ 0.883437] rtk_btcoex: alloc buffers 1792, 2432 for ev and l2 [ 0.889415] usbcore: registered new interface driver rtk_btusb [ 0.895541] sdhci: Secure Digital Host Controller Interface driver [ 0.901856] sdhci: Copyright(c) Pierre Ossman [ 0.906451] sdhci-pltfm: SDHCI platform and OF driver helper [ 0.912679] ledtrig-cpu: registered to indicate activity on CPUs [ 0.918992] usbcore: registered new interface driver usbhid [ 0.924704] usbhid: USB HID core driver [ 0.929126] optee: probing for conduit method from DT. [ 0.934390] optee: revision 3.7 (5208e5c1) [ 0.934538] optee: initialized driver [ 0.942715] mhi_init Quectel_Linux_PCIE_MHI_Driver_V1.2.0 [ 0.948691] NET: Registered protocol family 17 [ 0.953290] 9pnet: Installing 9P2000 support [ 0.957671] Key type dns_resolver registered [ 0.962264] registered taskstats version 1 [ 0.966451] Loading compiled-in X.509 certificates [ 0.975789] ti-sci 44083000.dmsc: ABI: 2.9 (firmware rev 0x0013 '19.12.1-v2019.12a (Terrific Lla') [ 1.000732] random: fast init done [ 1.036896] omap_i2c 40b00000.i2c: bus 0 rev0.12 at 400 kHz [ 1.042856] omap_i2c 40b10000.i2c: bus 1 rev0.12 at 100 kHz [ 1.048829] omap_i2c 42120000.i2c: bus 2 rev0.12 at 400 kHz [ 1.054794] omap_i2c 2000000.i2c: bus 3 rev0.12 at 400 kHz [ 1.060663] omap_i2c 2010000.i2c: bus 4 rev0.12 at 400 kHz [ 1.066541] omap_i2c 2020000.i2c: bus 5 rev0.12 at 400 kHz [ 1.072405] omap_i2c 2030000.i2c: bus 6 rev0.12 at 400 kHz [ 1.078255] omap_i2c 2040000.i2c: bus 7 rev0.12 at 100 kHz [ 1.084107] omap_i2c 2050000.i2c: bus 8 rev0.12 at 100 kHz [ 1.099080] cdns-torrent-phy 5050000.serdes: 4 lanes, max bit rate 5.400 Gbps [ 1.107935] cdns-pcie-host d000000.pcie: cdns_pcie_host_probe : pcie_3v3_enable : gpio_valid OK : ret=0 [ 1.117631] cdns-pcie-host d000000.pcie: cdns_pcie_host_probe : pcie_3v3_enable : gpio_request failed : ret=-517 [ 1.128159] cdns-pcie-host d000000.pcie: missing "mem" [ 1.133411] cdns-pcie-host d000000.pcie: cdns_pcie_host_probe : devm_gpiod_get_optional : GPIOD_OUT_LOW [ 11.324643] ti-sci 44083000.dmsc: Mbox timedout in resp(caller: ti_sci_cmd_get_device+0x20/0x38) [ 11.333629] ti-sci 44083000.dmsc: Mbox send fail -110 [ 12.092644] ti-sci 44083000.dmsc: Mbox timedout in resp(caller: ti_sci_cmd_put_device+0x20/0x38) [ 12.101629] ti-sci 44083000.dmsc: Mbox timedout in resp(caller: ti_sci_cmd_put_device+0x20/0x38) [ 12.110613] ti-sci 44083000.dmsc: Mbox timedout in resp(caller: ti_sci_cmd_put_device+0x20/0x38) [ 12.119596] ti-sci 44083000.dmsc: Mbox timedout in resp(caller: ti_sci_cmd_put_device+0x20/0x38) [ 12.128579] ti-sci 44083000.dmsc: Mbox timedout in resp(caller: ti_sci_cmd_put_device+0x20/0x38) [ 12.137562] ti-sci 44083000.dmsc: Mbox timedout in resp(caller: ti_sci_cmd_put_device+0x20/0x38) [ 12.146544] ti-sci 44083000.dmsc: Mbox timedout in resp(caller: ti_sci_cmd_put_device+0x20/0x38) [ 12.155526] ti-sci 44083000.dmsc: Mbox timedout in resp(caller: ti_sci_cmd_put_device+0x20/0x38) [ 12.164509] ti-sci 44083000.dmsc: Mbox send fail -110 [ 12.169671] ti-sci 44083000.dmsc: Mbox send fail -110 [ 12.174833] ti-sci 44083000.dmsc: Mbox send fail -110 [ 12.179995] ti-sci 44083000.dmsc: Mbox send fail -110 [ 12.185156] ti-sci 44083000.dmsc: Mbox send fail -110 [ 12.190318] ti-sci 44083000.dmsc: Mbox send fail -110 [ 12.195480] ti-sci 44083000.dmsc: Mbox send fail -110 [ 12.200641] ti-sci 44083000.dmsc: Mbox send fail -110 [ 12.348633] ti-sci 44083000.dmsc: Mbox timedout in resp(caller: ti_sci_cmd_put_device+0x20/0x38) [ 12.357615] ti-sci 44083000.dmsc: Mbox send fail -110 [ 21.564633] ti-sci 44083000.dmsc: Mbox timedout in resp(caller: ti_sci_cmd_get_device+0x20/0x38) [ 21.573613] ti-sci 44083000.dmsc: Mbox send fail -110 [ 31.804636] ti-sci 44083000.dmsc: Mbox timedout in resp(caller: ti_sci_cmd_get_resource_range+0x28/0x40) [ 31.814328] ti-sci 44083000.dmsc: Mbox send fail -110 [ 31.819490] k3-ringacc: probe of 2b800000.ringacc failed with error -22 [ 42.044638] ti-sci 44083000.dmsc: Mbox timedout in resp(caller: ti_sci_cmd_get_resource_range+0x28/0x40) [ 42.054330] ti-sci 44083000.dmsc: Mbox send fail -110 [ 42.059491] k3-ringacc: probe of 3c000000.ringacc failed with error -22
Thanks a lot!
Best Regard,
Leo Ho
Hi Leo Ho,
I will look at these and provide feedback. But just to state, there could be the following problems with loading this application as a firmware from u-boot along with linux:
1. The application doesn't load -> this can be fixed most likely by changing some memory map etc.
2. The application loads but uses some resource which needs to be used by linux, so when linux starts it expects that resource to be free and tries to access it, but then as that resource is bring used by R5 running the application, it could potentially cause a hang.
All this resource management is done by the Resource Manager inside the DMSC and hence the applications (already there in the /lib/firmware) abide by this and only use the resources assinged to their cores. Hence an application designed for standalone testing might not always run alongside linux if not tested.
Regards,
Karan
Hi Leo Ho,
I see your .vecs not in ATCM. It is in 0x41c40000
I was able to load the application till main() using the below linker file: After main() it is crashing.
/* linker options */
--fill_value=0
--stack_size=0x2000
--heap_size=0x1000
-e __VECS_ENTRY_POINT
MEMORY
{
MCU0_R5F_TCMA (X) : origin = 0x100 , length = 0x8000 - 0x100
RESET_VECTORS(X) : ORIGIN = 0x00000000 , LENGTH = 0x100 /* Bottom 256 KB used by SBL */
R5F_TCMB0(RWIX) : ORIGIN = 0x41010000 , LENGTH = 0x00008000
MSMC3(RWIX) : ORIGIN = 0x70080000 , LENGTH = 0x770000
DDR0(RWIX) : ORIGIN = 0x80000000 , LENGTH = 0x80000000
MCU1_0_MSRAM : origin = 0x41C40100 , length = 0x5C000 - 0x100
}
SECTIONS
{
.vecs : {
__VECS_ENTRY_POINT = .;
} palign(8) > RESET_VECTORS
.text_boot {
*boot.aer5f<*boot.o*>(.text)
} palign(8) > MCU0_R5F_TCMA
.text:xdc_runtime_Startup_reset__I : {} palign(8) > MCU0_R5F_TCMA
.text:ti_sysbios_family_arm_v7r_Cache* : {} palign(8) > MCU0_R5F_TCMA
.text:ti_sysbios_family_arm_MPU* : {} palign(8) > MCU0_R5F_TCMA
.rstvectors : {} palign(8) > MCU1_0_MSRAM
/* For NDK packet memory, we need to map this sectionsbefore .bss*/
.bss:NDK_MMBUFFER (NOLOAD) {} ALIGN (128) > MCU1_0_MSRAM
.bss:NDK_PACKETMEM (NOLOAD) {} ALIGN (128) > MCU1_0_MSRAM
.intvecs : {} palign(8) > MCU1_0_MSRAM
.bss : {} align(4) > MCU1_0_MSRAM
.text : {} palign(8) > MCU1_0_MSRAM
.cinit : {} palign(8) > MCU1_0_MSRAM
.bss : {} align(8) > MCU1_0_MSRAM
.far : {} align(8) > MCU1_0_MSRAM
.const : {} palign(8) > MCU1_0_MSRAM
.data : {} palign(128) > MCU1_0_MSRAM
.sysmem : {} align(8) > MCU1_0_MSRAM
.stack : {} align(4) > MCU1_0_MSRAM
.data_buffer: {} palign(128) > MCU1_0_MSRAM
}
Regards,
Karan
Hi Leo Ho,
Do you have a debugger on the custom board?
With my last reply (the linker cmd file I sent) the application is able to load from u-boot. I put a while(1) in the main and it hits, but after that the application is crashing, this is expected as the app in never validate with u-boot load so there might be some dependency which u-boot is not meeting.
Regards,
Karan
Hi Karan,
Sorry for late.
I have tried the linker cmd file, and it still no output log in any UART.
| Do you have a debugger on the custom board? |
Yes, we have debugger on the custom board now.
| I put a while(1) in the main and it hits |
I put the while in main have compiler error with it.
I have a quesiton.
When we follow the step to run the app https://e2e.ti.com/support/processors/f/791/t/902713 , the log will output on 2nd instance MCU UART, but we load the app from now is using 1st instance on MCU_UART, is there any conflict with app and UART?
Thanks a lot!
Best Regard,
Leo Ho
Hi Leo Ho,
leo ho said:When we follow the step to run the app https://e2e.ti.com/support/processors/f/791/t/902713 , the log will output on 2nd instance MCU UART, but we load the app from now is using 1st instance on MCU_UART, is there any conflict with app and UART?
I think that could be my mistake when I say 1st and 2nd UART.
To clarify:
MCU UART (J43) upon connecting will give you two UART instances:
0th - will give DMSC logs (if enabled)
1st - will give you application logs running on MCU R5F
In my earlier remarks I could have considered it like 1 & 2 instead of 0 & 1.
leo ho said:I put the while in main have compiler error with it.
Please refer the patch attached: /cfs-file/__key/communityserver-discussions-components-files/791/mcspi.patch
You can add the loop as:
diff --git a/packages/ti/drv/spi/example/mcspi_slavemode/src/main_mcspi_slave_mode.c b/packages/ti/drv/spi/example/mcspi_slavemode/src/main_mcspi_slave_mode.c
index 750aab3..6c6571d 100755
--- a/packages/ti/drv/spi/example/mcspi_slavemode/src/main_mcspi_slave_mode.c
+++ b/packages/ti/drv/spi/example/mcspi_slavemode/src/main_mcspi_slave_mode.c
@@ -1615,11 +1615,16 @@ void masterTaskFxn()
/*
* ======== main ========
*/
+volatile uint32_t qwerty = 0xDEADBEEF;
+
int main(void)
{
+ while(qwerty);
/* Call board init functions */
Board_initCfg boardCfg;
Board_STATUS boardStatus;
+ boardStatus = Board_init(BOARD_INIT_UART_STDIO);
+ SPI_log("\n congratulations! loaded from uboot brooo!\n");
#if defined (evmK2G)
SPI_v0_HWAttrs spi_cfg;
uint8_t instance;
The application has been loaded successfully as you have reached the main. But as I said I think that uboot is not taking care of some dependency hence the app is crashing later. There is an FAQ at - https://e2e.ti.com/support/processors/f/791/t/931992 which explains what can go wrong in such a case.
Regards,
Karan
Hi Karan,
Thanks for your reply.
I have tested the patch that you provide, and as you said it will crash after while().
Have a question, is the conflict with app and memory map or conflict with SPI and memory map?
Is it possible to use other spi app(e.g. ipc_spi_slave_demo_app) as SPI slave app on MCU1_0 for communicatie with external device (as master) and load from u-boot?
Best Regard,
Leo Ho
Hi Leo Ho,
leo ho said:Have a question, is the conflict with app and memory map or conflict with SPI and memory map?
Can you step through using CCS and see where the crash happens? That way we could get a little closer to the issue.
leo ho said:Is it possible to use other spi app(e.g. ipc_spi_slave_demo_app) as SPI slave app on MCU1_0 for communicatie with external device (as master) and load from u-boot?
I'm afraid but this application too is validated using CCS, might be the same issue here too.
Regards,
Karan
Hi Karan,
I load the app and press the "assembly step over" button, the process loop in "$C$L1126:".
I run in next line to exit the loop, and come up the error below the second configure.
Best Regard,
Leo Ho
Hi Leo Ho,
leo ho said:I load the app and press the "assembly step over" button, the process loop in "$C$L1126:".
I will try to do the same at my end, we need to look at the function causing the crash. We need to load the symbols for that.
Also, in the meantime will it be possible for you to use CCS for the validation?
leo ho said:We only run MCSPI slave app on MCU1_0 for communicatie with external device (as master).
I just realised, you want to run the slave app on the MCU1_0 or the master app? This app runs the master app on the MCU1_0 and slave on the MPU1_0 (A72)
Regards,
Karan
Hi Karan,
I will try to do the same at my end, we need to look at the function causing the crash. We need to load the symbols for that.
Also, in the meantime will it be possible for you to use CCS for the validation?
Yes, I can use CCS to validate, but the debugger will return to owner, so need to validate ASAP.
Is possible to fix the problem?
I just realised, you want to run the slave app on the MCU1_0 or the master app? This app runs the master app on the MCU1_0 and slave on the MPU1_0 (A72)
I want to run the slave app on the MCU1_0.
I know the original app is the master app on the MCU1_0, slave on the MPU1_0.
On this thread https://e2e.ti.com/support/processors/f/791/t/902713#pi320966=1, I have asked about using the slave app on MCU1_0 just need to verified corresponding code.
Best Regard,
Leo Ho
Hi Leo Ho,
I tried to debug and the code was failing at Board_init() for with BOARD_INIT_MODULE_CLOCK flag.
Also, the prints were not coming as the UART was not PINMUXed in the Master app. The Board_init() with BOARD_INIT_PINMUX_CONFIG was only done once and that was done as a part of the Slave app. You would see that in below code that pinmux was not happening if we run only the Master app. This makes sense when we run then together as both run on the same SoC and hence Pinmux doesn't need to happen twice.
#if defined(BUILD_MPU)
boardCfg = BOARD_INIT_PINMUX_CONFIG |
BOARD_INIT_MODULE_CLOCK |
BOARD_INIT_UART_STDIO;
#else
boardCfg = BOARD_INIT_MODULE_CLOCK |
BOARD_INIT_UART_STDIO;
#endif
So now if we disable the BOARD_INIT_MODULE_CLOCK (as the necessary modules are already enabled by SPL/u-boot) and then do the Pinmux by enabling the BOARD_INIT_PINMUX_CONFIG for the Master app (mcu1_0 build) then we see prints and also there is no crash.
#if defined(BUILD_MPU)
boardCfg = BOARD_INIT_UART_STDIO;
#else
boardCfg = BOARD_INIT_PINMUX_CONFIG |
BOARD_INIT_UART_STDIO;
#endif
The test however fails testcases as there is no slave running.
Please take the attached patch, this has the following:
1. Memory map changes to load using u-boot.
2. Board initiallization changes to enable pinmux and disable additional modules initiallization.
3. Removes the while(1) we added initially
4. Add prints just to validate the app in not crashing.
diff --git a/packages/ti/drv/spi/example/mcspi_slavemode/j721e/linker_mcu_sysbios.lds b/packages/ti/drv/spi/example/mcspi_slavemode/j721e/linker_mcu_sysbios.lds
index 9acf400..c2e278e 100644
--- a/packages/ti/drv/spi/example/mcspi_slavemode/j721e/linker_mcu_sysbios.lds
+++ b/packages/ti/drv/spi/example/mcspi_slavemode/j721e/linker_mcu_sysbios.lds
@@ -7,11 +7,12 @@
MEMORY
{
- R5F_TCMA_SBL_RSVD(X): ORIGIN = 0x00000000 , LENGTH = 0x100
- RESET_VECTORS(X) : ORIGIN = 0x41c40000 , LENGTH = 0x100 /* Bottom 256 KB used by SBL */
- R5F_TCMB0(RWIX) : ORIGIN = 0x41010000 , LENGTH = 0x00008000
- MSMC3(RWIX) : ORIGIN = 0x70080000 , LENGTH = 0x770000
- DDR0(RWIX) : ORIGIN = 0x80000000 , LENGTH = 0x80000000
+ MCU0_R5F_TCMA (X) : origin = 0x100 , length = 0x8000 - 0x100
+ RESET_VECTORS(X) : ORIGIN = 0x00000000 , LENGTH = 0x100 /* Bottom 256 KB used by SBL */
+ R5F_TCMB0(RWIX) : ORIGIN = 0x41010000 , LENGTH = 0x00008000
+ MSMC3(RWIX) : ORIGIN = 0x70080000 , LENGTH = 0x770000
+ DDR0(RWIX) : ORIGIN = 0x80000000 , LENGTH = 0x80000000
+ MCU1_0_MSRAM : origin = 0x41C40100 , length = 0x5C000 - 0x100
}
SECTIONS
@@ -21,18 +22,25 @@ SECTIONS
} palign(8) > RESET_VECTORS
.text_boot {
*boot.aer5f<*boot.o*>(.text)
- } palign(8) > R5F_TCMB0
- .text:xdc_runtime_Startup_reset__I : {} palign(8) > R5F_TCMB0
- .text:ti_sysbios_family_arm_v7r_Cache* : {} palign(8) > R5F_TCMB0
- .text:ti_sysbios_family_arm_MPU* : {} palign(8) > R5F_TCMB0
+ } palign(8) > MCU0_R5F_TCMA
+ .text:xdc_runtime_Startup_reset__I : {} palign(8) > MCU0_R5F_TCMA
+ .text:ti_sysbios_family_arm_v7r_Cache* : {} palign(8) > MCU0_R5F_TCMA
+ .text:ti_sysbios_family_arm_MPU* : {} palign(8) > MCU0_R5F_TCMA
+ .rstvectors : {} palign(8) > MCU1_0_MSRAM
- .text : {} palign(8) > MSMC3
- .cinit : {} palign(8) > MSMC3
- .bss : {} align(8) > MSMC3
- .far : {} align(8) > MSMC3
- .const : {} palign(8) > MSMC3
- .data : {} palign(128) > MSMC3
- .sysmem : {} align(8) > MSMC3
- .stack : {} align(4) > MSMC3
- .data_buffer: {} palign(128) > DDR0
+ /* For NDK packet memory, we need to map this sectionsbefore .bss*/
+ .bss:NDK_MMBUFFER (NOLOAD) {} ALIGN (128) > MCU1_0_MSRAM
+ .bss:NDK_PACKETMEM (NOLOAD) {} ALIGN (128) > MCU1_0_MSRAM
+
+ .intvecs : {} palign(8) > MCU1_0_MSRAM
+ .bss : {} align(4) > MCU1_0_MSRAM
+ .text : {} palign(8) > MCU1_0_MSRAM
+ .cinit : {} palign(8) > MCU1_0_MSRAM
+ .bss : {} align(8) > MCU1_0_MSRAM
+ .far : {} align(8) > MCU1_0_MSRAM
+ .const : {} palign(8) > MCU1_0_MSRAM
+ .data : {} palign(128) > MCU1_0_MSRAM
+ .sysmem : {} align(8) > MCU1_0_MSRAM
+ .stack : {} align(4) > MCU1_0_MSRAM
+ .data_buffer: {} palign(128) > MCU1_0_MSRAM
}
diff --git a/packages/ti/drv/spi/example/mcspi_slavemode/src/main_mcspi_slave_mode.c b/packages/ti/drv/spi/example/mcspi_slavemode/src/main_mcspi_slave_mode.c
index 750aab3..4a25e03 100755
--- a/packages/ti/drv/spi/example/mcspi_slavemode/src/main_mcspi_slave_mode.c
+++ b/packages/ti/drv/spi/example/mcspi_slavemode/src/main_mcspi_slave_mode.c
@@ -1563,11 +1563,14 @@ Void masterTaskFxn (UArg arg0, UArg arg1)
void masterTaskFxn()
#endif
{
+ SPI_log("\n < ---- Inside Master Task ---- > \n");
uint32_t i;
bool testFail = false;
SPI_Tests *test;
+ SPI_log("\n < ---- SPI_init() ---- > \n");
SPI_init();
+ SPI_log("\n < ---- SPI_init() ...done ---- > \n");
for (i = 0; ; i++)
{
@@ -1615,11 +1618,15 @@ void masterTaskFxn()
/*
* ======== main ========
*/
+volatile uint32_t qwerty = 0x0;
+
int main(void)
{
+ while(qwerty);
/* Call board init functions */
Board_initCfg boardCfg;
Board_STATUS boardStatus;
+ boardStatus = Board_init(BOARD_INIT_UART_STDIO);
#if defined (evmK2G)
SPI_v0_HWAttrs spi_cfg;
uint8_t instance;
@@ -1667,14 +1674,18 @@ int main(void)
* pinmux only need to be initialized once in board
*/
#if defined(BUILD_MPU)
- boardCfg = BOARD_INIT_PINMUX_CONFIG |
- BOARD_INIT_MODULE_CLOCK |
- BOARD_INIT_UART_STDIO;
+ //boardCfg = BOARD_INIT_MODULE_CLOCK |
+ // BOARD_INIT_UART_STDIO;
+ boardCfg = BOARD_INIT_UART_STDIO;
#else
- boardCfg = BOARD_INIT_MODULE_CLOCK |
+ //boardCfg = BOARD_INIT_PINMUX_CONFIG |
+ // BOARD_INIT_MODULE_CLOCK |
+ // BOARD_INIT_UART_STDIO;
+ boardCfg = BOARD_INIT_PINMUX_CONFIG |
BOARD_INIT_UART_STDIO;
#endif
boardStatus = Board_init(boardCfg);
+ SPI_log("\n < ---- Board_init ...done ---- > \n");
if (boardStatus != BOARD_SOK)
{
return (0);
Patch: /cfs-file/__key/communityserver-discussions-components-files/791/mcspi_5F00_mcu1_5F00_0.patch
Binary of the executable: /cfs-file/__key/communityserver-discussions-components-files/791/MCSPI_5F00_MasterSlave_5F00_j721e_5F00_evm_5F00_mcu1_5F00_0TestApp_5F00_release.zip
Logs I got on the MCU UART (1st instance out of 0 & 1)
< ---- Board_init ...done ---- > < ---- Inside Master Task ---- > < ---- SPI_init() ---- > < ---- SPI_init() ...done ---- > SPI UT 1 SPI master slave test master in non-dma interrupt mode SPI initialized SPI master slave test master in non-dma interrupt mode have failed Some tests have failed. Done
Please let me know if this works for you. There is no need to connect the debugger, just load using the old method you were using at u-boot prompt.
Regards,
Karan
Hi Karan,
The app can load from u-boot and have output log.
Thanks for your help!
Best Regard,
Leo Ho