TDA2EVM5777: how to improve latency on TIDL(SSD) application?

user6065254

Part Number: TDA2EVM5777
Other Parts Discussed in Thread: TDA2

Hi experts:

I developed my application by using tidl(SSD) to detect object on image and followed the default TIDL use-case for SSD application on RTOS.

After dumping message from TDA2-evm-board, i noticed that the TDA2-evm-board was running on 27-fps but the latency was up to 173ms (average latency time from capture to display link).

Full log from TDA2-board is here:latency-log.txt

i'm wondering:

1. why does the 27-fps speed have 173 ms latency? why the latency is not 1000/27=37 ms?

2. how to improve latency down to 1000/30=33 ms?

Please comment, Thank you.

Best / regards

wxchen

over 5 years ago

0 Gaviraju Doddabettahalli Bettegowda over 5 years ago

TI__Genius 14305 points

Hi,

.1) why does the 27-fps speed have 173 ms latency? why the latency is not 1000/27=37 ms?

In VSDK all links are running parallel & because of this, you are able to achieve 27FPS.

suppose if all the links are running sequentially then

FPS = 1000/173

FPS = 5

2) how to improve latency down to 1000/30=33 ms?

it's not possible because the TIDL link itself taking around 130ms to process

Thanks

Gaviraju

0 user6065254 over 5 years ago in reply to Gaviraju Doddabettahalli Bettegowda

Intellectual 390 points

Hi,

Thanks for your response.

I'm curious about the 130ms you mentioned.

How does the 130ms come? Is it limit of SSD-model running on TDA2 platform?

Thanks

Best / regards

wxchen

0 Gaviraju Doddabettahalli Bettegowda over 5 years ago in reply to user6065254

TI__Genius 14305 points

Hi,

The time is taken by the TIDL algorithm is 130ms to process one frame

In order to reduce the latency, you should optimize the TIDL algorithm & the source code of these algorithms is not available in the vision SDK(We used library in vision SDK).

Please check with the TI sales team to get the source code.

Thanks

Gaviraju

0 user6065254 over 5 years ago in reply to Gaviraju Doddabettahalli Bettegowda

Intellectual 390 points

Hi,

I believe that the TIDL algorithm had been optimized by TI's RnD team.

Is there another idea to reduce latency?

Thanks,

Best / Regards

Wxchen

0 Gaviraju Doddabettahalli Bettegowda over 5 years ago in reply to user6065254

TI__Genius 14305 points

No other way to reduce the latency.

0 user6065254 over 5 years ago in reply to Gaviraju Doddabettahalli Bettegowda

Intellectual 390 points

Hi,

Thanks for your response.

In addition, you said "optimize the TIDL algorithm" in your previous post.

I'm wondering what should I optimize?

In my intuition, I should optimize the tidl on EVE to process convolution-like operations. Is it correct?

Or you mean that I should optimize the SSD's network architecture or others?

Thanks.

Best / Regards

Wxchen

0 Praveen Eppa1 over 5 years ago in reply to user6065254

TI__Genius 17580 points

Hi Wxchen,

The tidl on EVE is already fully optimized, you can try optimizing your SSD network architecture.

Thanks,

Praveen

0 user6065254 over 5 years ago in reply to Praveen Eppa1

Intellectual 390 points

Hi,

Thanks for your response.

I'm using jacintoV2 network currently.

Do you have any suggestion/experience for optimizing SSD network architecture?

Thanks.

Best / Regards

Wxchen

0 kumar.desappan over 5 years ago in reply to user6065254

TI__Mastermind 22145 points

Hi Wxchen,

You can either reduce the resolution or train your SSD network with less complex backbone networks like mobile net v1 with a depth multiplier 0.25

Currently, we do not have a pre-trained network example for such models in SDK.

Regards,

Kumar.D

0 user6065254 over 5 years ago in reply to kumar.desappan

Intellectual 390 points

Hi:

Thanks for your response.

I will try to decrease SSD network architecture according to your advises.

However, I wanna ask for tda2's hardware:

1: Is it possible to boost the clock rate in EVE-core to improve latency? if yes, how to do that? any suggestion for doing that?

2: On the other hand, as far I know, ti's tda4 platform is going to release,

2-1: is that platform capable to reach 1000/30=33ms latency time in jacintoSSD network application?

2.2: is that platform using the same VSDK to tda2's plaform?

Thanks,

Best / Regards

Wxchen

0 Praveen Eppa1 over 5 years ago in reply to user6065254

TI__Genius 17580 points

Hi Wxchen,

1. No, as EVE core already clocked at max capacity so no further increase is possible.

2. Yes, but tda4 comes with new sdk, please read more about tidl in tda4 here

https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/tidl_j7_01_02_00_09/ti_dl/docs/user_guide_html/md_tidl_models_info.html

Thanks,

Praveen

Processors

Processors forum

TDA2EVM5777: how to improve latency on TIDL(SSD) application?