Part Number: TDA4VMXEVM
Tool/software: TI C/C++ Compiler
Hi:
We configured an interrupt, routed from CLEC to GIC500, and finally processed by A72。As described in the technical manual，CLEC will maintain pending interrupt information in CLEC_EFR_j register, and fireware needs to clear this pending interrupt bit.
As described in http://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721e/firewalls.html. which allows C71/C66/R5 to access these registers.But in A72, accessing to the CLEC_ESR_j / CLEC_ECR_j register will lead to the following error:
ERROR: Unhandled External Abort received on 0x80000001 at EL3!
ERROR: exception reason=0 syndrome=0xbf000000
PANIC in EL3.
So, what should we do, if we want to access CLEC_ESR_j / CLEC_ECR_j or clear this CLEC pending interrupt bit?
