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Apart from the TRM: www.ti.com/.../spruil1, is there a cheat sheet to choosing the right OSPI part for my custom board based on Jacinto 7?
The Jacinto 7 supports a wide variety of OSPI parts and almost a large subset should be compatible.
Please use the following additional information while deciding the OSPI part for the custom device based on Jacinto 7.
For a flash to be supported in Linux and U-Boot, the below requirements should be met:
For AM62/AM64/AM243/TDA4VL/TDA4AL/J721s2: Please check errata list for errata "i2366": E.g. https://www.ti.com/lit/pdf/sprz530.
The command opcodes and protocols vary from one flash vendor to another. In summary, the following commands need to be supported with their opcodes and protocols. More details are provided below.
|
Command
|
Opcode
|
Protocol
|
Dummy Cycles
|
Address Bytes
|
|---|---|---|---|---|
| Read ID | 0x9F | 1S-1S-1S (same as 1-0-1) | 0 | 0 |
| Read SFDP | 0x5A | 1S-1S-1S | 8 | 3 |
| Read Flash Array | 1S-1S-1S/1S-1S-8S/8D-8D-8D | 3 or 4 (1S-1S-1S / 1S-1S-8S) / 4 (8D-8D-8D) | ||
| Read Status Register | 0x05 | 1S-1S-1S/8D-8D-8D | 0 (1S-1S-1S) / Any (8D-8D-8D) | 0 (1S-1S-1S) / 0 or 4 (8D-8D-8D) 1 |
| Write Enable | 0x06 | 1S-1S-1S/8D-8D-8D | 0 | 0 |
| Erase Sector | 1S-1S-1S/8D-8D-8D | 0 | 3 or 4 (1S-1S-1S) / 4 (8D-8D-8D) | |
| Page Program | 1S-1S-1S/1S-1S-8S/8D-8D-8D | 0 | 3 or 4 (1S-1S-1S) / 4 (8D-8D-8D) | |
| Software Reset Sequence | 0x66, 0x99 | 8D-8D-8D | 0 | 0 |
Note: In rows where no opcode is specified, the opcode is flexible and can be varied depending on the flash vendor. For example, for "Read Flash Array", Micron uses opcode 0xFD and Cypress uses opcode 0xEE in 8D-8D-8D mode.
1. The value of the address should be 0.
This command reads the ID stored on the flash and is used for identifying the flash model. It is the first command that is issued when a flash is probed. This command is mandatory for supporting a flash. It needs to have the opcode 0x9F, 0 address bytes, 0 dummy bytes, and 1S-1S-1S protocol.
This command reads the SFDP data from the flash and can be used to discover what opcodes and protocols the flash supports. While it is not mandatory for supporting a flash, it is highly recommended because it reduces the burden on software to manually configure all the parameters of a flash. The command should use the opcode 0x5A, 3 address bytes, 8 dummy cycles, and 1S-1S-1S protocol.
Some flashes support this command in 8D-8D-8D mode or have a different dummy cycles for it. These commands cannot be used because of the way the flash driver is written.
This command is used for reading data from the flash. This command usually has different opcodes and protocols between different vendors. Currently, these commands can use 1S-1S-1S, 1S-1S-8S, 1S-8S-8S (not tested), or 8D-8D-8D protocol. They can have different opcodes and address bytes, and dummy cycles depending on the vendor.
This command is used for reading the status of the flash and checking whether the write or erase operations in progress have finished or not. It is mandatory for a flash to support this command in 1S-1S-1S mode with the opcode 0x05, 0 address bytes, 0 dummy cycles. The status register should at the very least contain the "Write in Progress" status at bit 0 in the register.
If erases or writes are to be used in 8D-8D-8D mode, this command should also be supported in 8D-8D-8D mode with opcode 0x05. Optionally, 4 dummy address bytes (all 0x00) and any number of dummy cycles can be used.
The write enable command enables write operations on the flash. It is mandatory for a flash to support this command in 1S-1S-1S mode with the opcode 0x06, 0 address bytes, 0 dummy cycles, 0 data bytes.
If erases or writes are to be used in 8D-8D-8D mode, this command should also be supported in 8D-8D-8D mode with opcode 0x06, 0 address bytes, 0 dummy cycles.
Before data can be programmed on a flash, the region has to be erased. A flash that needs to support writes has to support an erase command. The erase command can have any opcode as specified by the flash vendor, 3 or 4 address bytes depending on the flash configuration, and 0 dummy cycles in 1S-1S-1S protocol.
If erases or writes are to be used in 8D-8D-8D mode, this command should also be supported in 8D-8D-8D mode with 4 address bytes and 0 dummy cycles.
This command is used to write data on the flash memory. A flash that needs to support writes has to support this command. It can have any opcode as specified by the flash vendor, 3 or 4 address bytes depending on the flash configuration, and 0 dummy cycles in 1S-1S-1S or 1S-1S-8S protocol.
If writes are to be used in 8D-8D-8D mode, this command should also be supported in 8D-8D-8D mode with 4 address bytes and 0 dummy cycles.
The Software Reset Sequence consists of two commands, Reset Enable (opcode 0x66) and Software Reset (opcode 0x99). It resets the flash to its Power-on-Reset state. It is mandatory if 8D-8D-8D mode is to be used. The sequence is executed in 8D-8D-8D mode with no address, dummy, or data cycles with command opcode extension as "Repeat". It should ideally take less than 100ms to finish but that is not a hard limit.
Linux and U-Boot support multiple OSPI flashes. The following combinations of flash and board have been successfully tested:
|
Flash Name
|
Boards tested on
|
|---|---|
| Cypress S28HS512TGABHM010 | J721E*, J7200 |
| Micron MT35XU512ABA1G12-0AAT | J721E, AM654 |
* S28HS512TGABHM010 will not work on J721E SR1.0 out of the box.
Other variants of the above flash families have not been tested yet. Check compatibility as above.
Suppose there is a flash which uses the opcode 0x21 for its Read ID command. The Read ID command can only have the opcode 0x9F. So this flash would not be supported.
Suppose there is a flash which uses 4 address bytes for the Read SFDP command in 1S-1S-1S mode. The Read SFDP command can only use 3 address bytes. Such a flash would not be supported.
Suppose there is a flash which boots by default in DDR x8 mode, such a flash would not be supported.
Example: MT35XU01GBBA2G12
