[DRA829]How does XIP work when using multiple cores

Hi Xie,

Linda Xie said:

1. We are using multiple cores using the same code (SMP).We only need to control the SBL to jump to the entry address of the main core, and then the Slave Core is started through the Main Core？Does additional processing need to be done?

R5F dual core cannot support SMP mode as both the cores do not have a unified view of memory. So this situation will not be possible.

Linda Xie said:

2. If we use different bin files for each core，How should we control jump to different core entry addresses to start applications（NO SMP）? In this case, each core should access OSPI to obtain the execution instructions of the code. This should cause resource access conflicts. How to solve this problem?

I haven't seen this being tested (atleast in the SDK). But SBL supports loading a multicore images, for the mcu1_0 it could be like a jump to application (where there is no reset to mcu1_0 as the SBL also is running on the same core) but for mcu1_1 I'm thinking that this needs to be first loaded by the application SBL with the application and then and then run. Going through a whole reset even if we are able to run in XIP - how much of a boost in startup time will remain, I'm not sure.

Can you help me understand the use case here? Why are you looking for mcu1_1 and mcu1_0 both running from xip? Is this with respect to space you are trying to save or quick startup time you want?

Regards,

Karan

Hi,Karan,

Karan Saxena said:

but for mcu1_1 I'm thinking that this needs to be first loaded by the application and then run

What you mean by "first loaded by the application and then run" is MCU1_0 to download MCU1_1 image to DDR4 or SRAM?

Our current design is not to use DDR4, and then all Cores use XIP mode, So the startup method of MCU1_1 you mentioned may not be applicable。

Karan Saxena said:

Can you help me understand the use case here? Why are you looking for mcu1_1 and mcu1_0 both running from xip? Is this with respect to space you are trying to save or quick startup time you want?

As mentioned above, our hardware design does not use DDR4, and XIP can also save startup time.

Please point out if there is any detail that I said

Regards,

Xie

Hi Xie,

I get the intention now. The main intent is mainly to avoid DDR. 

So to clarify my previous point. For MCU1_0 running in XIP - we see that the SBL can directly jump to the application (without issuing a reset to the MCU1_0 core) as the MCU 1_0 core is already powered on and is running.

This is different from the MCU1_1 case. As the MCU1_1 is not yet powered on, so the SBL will need to do all the initializations and then load the targeted application on to MCU1_1 and then issue a reset. So the KPI of startup time might now be met here. 

Regards,

Karan

Hi,Karan，

When I saw the last jump in the SBL_main.c file, I jumped to 0x0 through MCU1_CPU1，as shown below：Why not through MCU1_CPU0?

Then how does the multi-core core get instructions from Nor flash through an OSPI to run? How to avoid hardware resource conflicts caused by simultaneous access of multiple cores?

Regards,

Xie

Hi Xie,

There are some discussions happening internally. I will summarize them once we have more clarity. Meanwhile you can ask for the current status from Fan Zhang.

Regards,

Karan