Part Number: AM5728
Other Parts Discussed in Thread: TLV320AIC3254,
We have a custom board with TLV320AIC3254 audio codec connected to MCASP4 pins of AM5728.
AM5728 TL320AIC2354 AHCLKX |C23 >---------------> 1| MCLK ACLKX |C18 <---------------< 2| BCLK FSX |A21 <---------------< 3| WCLK AXR0 |G16 >---------------> 4| DIN AXR1 |D17 <---------------< 5| DOUT
McASP’s transmit and receive clocking sections are intended to operate synchronously (ASYNC=0), codec is clock and frame master (SND_SOC_DAIFMT_CBM_CFM).
The problem is that with the davinci-mcasp driver implementation provided with SDK 06.03 (4.19.94-gbe5389fd85) the RX secеion is not working in our case; when executing arecord command I see that RX clocks are not being aсtivated.
There is 'mcasp_is_synchronous' function which is used among the davinci-mcasp.c code.
static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
{
u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
}
AFSRE corresponds to AFSRCTL.FSRM which is:
Receive frame sync generation select bit.
0 Externally-generated receive frame sync
1 Internally-generated receive frame sync
The main question is why SYNC mode is only allowed with AFSRCTL.FSRM bit set (internally generated RX frame sync)?! Is it not possible to have both external codec as a frame master and SYNC mode?
According to SPRU041J Figure 2-4. Frame Sync Generator Block Diagram FSRM is ignored when ASYNC(ACLKXCTL.6) == 0
Removing AFSRE check does help, at least I don't see any negative side effects, arecord, aplay, arecord | aplay ALSA commands are working well.
static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
{
u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
return !(aclkxctl & TX_ASYNC);
}
Please consider applying this fix in next sdk releases.
