TDA4VM: Run mcan_test application on MCU1_0 Problem. Can not read or write register.

/**
 *  \file     mcan_test.c
 *
 *  \brief    This file contains MCAN sample code.
 *
 *  Targeted Functionality: Verifying the transmit and receive functionality
 *    of MCAN module.
 *
 *  Operation: MCAN operational mode is set to CAN-FD. This test will need
 *  two MCAN ports.
 *
 *  Supported SoCs: AM65XX, J721E, J7200,AM64x.
 *
 *  Supported Platforms: am65xx_idk, j721e_evm, j7200_evm, am64x_evm.
 *
 */

#include "mcan_test_priv.h"
#define MCAN_DEBUG
//#define PRODUCT

volatile uint32_t gMcanIsrIntr0Flag = 1U;
volatile uint32_t gMcanIsrIntr1Flag = 1U;

uint32_t mcanMaxPorts = 0;

BoardDiag_McanPortInfo_t gMcanDiagPortInfo[MCAN_MAX_PORTS_EXP] =
    {
        {CSL_MCU_MCAN0_MSGMEM_RAM_BASE, 0, MCU_MCAN0_TX_INT_NUM, MCU_MCAN0_RX_INT_NUM, MCU_MCAN0_TS_INT_NUM},
        {CSL_MCU_MCAN1_MSGMEM_RAM_BASE, 1, MCU_MCAN1_TX_INT_NUM, MCU_MCAN1_RX_INT_NUM, MCU_MCAN1_TS_INT_NUM},
        {CSL_MCAN0_MSGMEM_RAM_BASE, 0, MAIN_MCAN0_TX_INT_NUM, MAIN_MCAN0_RX_INT_NUM, MAIN_MCAN0_TS_INT_NUM},
        {CSL_MCAN1_MSGMEM_RAM_BASE, 1, MAIN_MCAN1_TX_INT_NUM, MAIN_MCAN1_RX_INT_NUM, MAIN_MCAN1_TS_INT_NUM},
        {CSL_MCAN2_MSGMEM_RAM_BASE, 2, MAIN_MCAN2_TX_INT_NUM, MAIN_MCAN2_RX_INT_NUM, MAIN_MCAN2_TS_INT_NUM},
        {CSL_MCAN3_MSGMEM_RAM_BASE, 3, MAIN_MCAN3_TX_INT_NUM, MAIN_MCAN3_RX_INT_NUM, MAIN_MCAN3_TS_INT_NUM},
        {CSL_MCAN4_MSGMEM_RAM_BASE, 4, MAIN_MCAN4_TX_INT_NUM, MAIN_MCAN4_RX_INT_NUM, MAIN_MCAN4_TS_INT_NUM},
        {CSL_MCAN5_MSGMEM_RAM_BASE, 5, MAIN_MCAN5_TX_INT_NUM, MAIN_MCAN5_RX_INT_NUM, MAIN_MCAN5_TS_INT_NUM},
        {CSL_MCAN6_MSGMEM_RAM_BASE, 6, MAIN_MCAN6_TX_INT_NUM, MAIN_MCAN6_RX_INT_NUM, MAIN_MCAN6_TS_INT_NUM},
        {CSL_MCAN7_MSGMEM_RAM_BASE, 7, MAIN_MCAN7_TX_INT_NUM, MAIN_MCAN7_RX_INT_NUM, MAIN_MCAN7_TS_INT_NUM},
        {CSL_MCAN8_MSGMEM_RAM_BASE, 8, MAIN_MCAN8_TX_INT_NUM, MAIN_MCAN8_RX_INT_NUM, MAIN_MCAN8_TS_INT_NUM},
        {CSL_MCAN9_MSGMEM_RAM_BASE, 9, MAIN_MCAN9_TX_INT_NUM, MAIN_MCAN9_RX_INT_NUM, MAIN_MCAN9_TS_INT_NUM},
        {CSL_MCAN10_MSGMEM_RAM_BASE, 10, MAIN_MCAN10_TX_INT_NUM, MAIN_MCAN10_RX_INT_NUM, MAIN_MCAN10_TS_INT_NUM},
        {CSL_MCAN11_MSGMEM_RAM_BASE, 11, MAIN_MCAN11_TX_INT_NUM, MAIN_MCAN11_RX_INT_NUM, MAIN_MCAN11_TS_INT_NUM},
        {CSL_MCAN12_MSGMEM_RAM_BASE, 12, MAIN_MCAN12_TX_INT_NUM, MAIN_MCAN12_RX_INT_NUM, MAIN_MCAN12_TS_INT_NUM},
        {CSL_MCAN13_MSGMEM_RAM_BASE, 13, MAIN_MCAN13_TX_INT_NUM, MAIN_MCAN13_RX_INT_NUM, MAIN_MCAN13_TS_INT_NUM}};

/* GPIO Driver board specific pin configuration structure */
GPIO_PinConfig gpioPinConfigs[] = {
    MCU_CAN0_STB_PIN | GPIO_CFG_OUTPUT,
    MCU_CAN1_STB_PIN | GPIO_CFG_OUTPUT,
};

/* GPIO Driver call back functions */
GPIO_CallbackFxn gpioCallbackFunctions[] = {
    NULL};

/* GPIO Driver configuration structure */
GPIO_v0_Config GPIO_v0_config = {
    gpioPinConfigs,
    gpioCallbackFunctions,
    sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
    sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
    0,
};

#ifdef MCAN_DEBUG

typedef struct MCAN_OffsetAddr_t
{
    int32_t mcanSsOffset;
    int32_t mcanCfgOffset;
} MCAN_OffsetAddr;
#if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_J7200)
/* User will provide only the MsgRam Base address.
 * All Offsets are calculated compared to MsgRam Base address. */
static const MCAN_OffsetAddr mcuMcanOffsetAddr = {
    .mcanSsOffset = ((int32_t)CSL_MCU_MCAN0_SS_BASE - (int32_t)CSL_MCU_MCAN0_MSGMEM_RAM_BASE),
    .mcanCfgOffset = ((int32_t)CSL_MCU_MCAN0_CFG_BASE - (int32_t)CSL_MCU_MCAN0_MSGMEM_RAM_BASE),
};
/* Offsets are same for MCU MCAN0 and MCU MCAN1 instances. */
#if (((CSL_MCU_MCAN0_SS_BASE - CSL_MCU_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCU_MCAN1_SS_BASE - CSL_MCU_MCAN1_MSGMEM_RAM_BASE)) || \
     ((CSL_MCU_MCAN0_CFG_BASE - CSL_MCU_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCU_MCAN1_CFG_BASE - CSL_MCU_MCAN1_MSGMEM_RAM_BASE)))
#error Offsets assumed donot match for MCU MCAN1
#endif
#endif

#if defined(SOC_J721E) || defined(SOC_J7200)
/* User will provide only the MsgRam Base address.
 * All Offsets are calculated compared to MsgRam Base address. */
static const MCAN_OffsetAddr mainMcanOffsetAddr = {
    .mcanSsOffset = ((int32_t)CSL_MCAN0_SS_BASE - (int32_t)CSL_MCAN0_MSGMEM_RAM_BASE),
    .mcanCfgOffset = ((int32_t)CSL_MCAN0_CFG_BASE - (int32_t)CSL_MCAN0_MSGMEM_RAM_BASE),
};

/* Offsets are same for all main domain instances MCAN0 to MCAN13. For J7VCL it is MCAN0 to MCAN17 */
#if (((CSL_MCAN0_SS_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN1_SS_BASE - CSL_MCAN1_MSGMEM_RAM_BASE)) || \
     ((CSL_MCAN0_CFG_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN1_CFG_BASE - CSL_MCAN1_MSGMEM_RAM_BASE)))
#error Offsets assumed donot match for MCAN1
#endif
#if (((CSL_MCAN0_SS_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN2_SS_BASE - CSL_MCAN2_MSGMEM_RAM_BASE)) || \
     ((CSL_MCAN0_CFG_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN2_CFG_BASE - CSL_MCAN2_MSGMEM_RAM_BASE)))
#error Offsets assumed donot match for MCAN21
#endif
#if (((CSL_MCAN0_SS_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN3_SS_BASE - CSL_MCAN3_MSGMEM_RAM_BASE)) || \
     ((CSL_MCAN0_CFG_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN3_CFG_BASE - CSL_MCAN3_MSGMEM_RAM_BASE)))
#error Offsets assumed donot match for MCAN3
#endif
#if (((CSL_MCAN0_SS_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN4_SS_BASE - CSL_MCAN4_MSGMEM_RAM_BASE)) || \
     ((CSL_MCAN0_CFG_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN4_CFG_BASE - CSL_MCAN4_MSGMEM_RAM_BASE)))
#error Offsets assumed donot match for MCAN4
#endif
#if (((CSL_MCAN0_SS_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN5_SS_BASE - CSL_MCAN5_MSGMEM_RAM_BASE)) || \
     ((CSL_MCAN0_CFG_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN5_CFG_BASE - CSL_MCAN5_MSGMEM_RAM_BASE)))
#error Offsets assumed donot match for MCAN5
#endif
#if (((CSL_MCAN0_SS_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN6_SS_BASE - CSL_MCAN6_MSGMEM_RAM_BASE)) || \
     ((CSL_MCAN0_CFG_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN6_CFG_BASE - CSL_MCAN6_MSGMEM_RAM_BASE)))
#error Offsets assumed donot match for MCAN6
#endif
#if (((CSL_MCAN0_SS_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN7_SS_BASE - CSL_MCAN7_MSGMEM_RAM_BASE)) || \
     ((CSL_MCAN0_CFG_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN7_CFG_BASE - CSL_MCAN7_MSGMEM_RAM_BASE)))
#error Offsets assumed donot match for MCAN7
#endif
#if (((CSL_MCAN0_SS_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN8_SS_BASE - CSL_MCAN8_MSGMEM_RAM_BASE)) || \
     ((CSL_MCAN0_CFG_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN8_CFG_BASE - CSL_MCAN8_MSGMEM_RAM_BASE)))
#error Offsets assumed donot match for MCAN8
#endif
#if (((CSL_MCAN0_SS_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN9_SS_BASE - CSL_MCAN9_MSGMEM_RAM_BASE)) || \
     ((CSL_MCAN0_CFG_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN9_CFG_BASE - CSL_MCAN9_MSGMEM_RAM_BASE)))
#error Offsets assumed donot match for MCAN9
#endif
#if (((CSL_MCAN0_SS_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN10_SS_BASE - CSL_MCAN10_MSGMEM_RAM_BASE)) || \
     ((CSL_MCAN0_CFG_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN10_CFG_BASE - CSL_MCAN10_MSGMEM_RAM_BASE)))
#error Offsets assumed donot match for MCAN10
#endif
#if (((CSL_MCAN0_SS_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN11_SS_BASE - CSL_MCAN11_MSGMEM_RAM_BASE)) || \
     ((CSL_MCAN0_CFG_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN11_CFG_BASE - CSL_MCAN11_MSGMEM_RAM_BASE)))
#error Offsets assumed donot match for MCAN11
#endif
#if (((CSL_MCAN0_SS_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN12_SS_BASE - CSL_MCAN12_MSGMEM_RAM_BASE)) || \
     ((CSL_MCAN0_CFG_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN12_CFG_BASE - CSL_MCAN12_MSGMEM_RAM_BASE)))
#error Offsets assumed donot match for MCAN12
#endif
#if (((CSL_MCAN0_SS_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN13_SS_BASE - CSL_MCAN13_MSGMEM_RAM_BASE)) || \
     ((CSL_MCAN0_CFG_BASE - CSL_MCAN0_MSGMEM_RAM_BASE) != (CSL_MCAN13_CFG_BASE - CSL_MCAN13_MSGMEM_RAM_BASE)))
#error Offsets assumed donot match for MCAN13
#endif
#endif /* #if defined (SOC_J721E) || defined (SOC_J7200) */

static const MCAN_OffsetAddr *MCAN_getOffsetAddr(uint32_t baseAddr)
{
    const MCAN_OffsetAddr *offsetAddr;
    switch ((uint64_t)baseAddr)
    {
#if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_AM77X) || defined(SOC_J7200)
    case CSL_MCU_MCAN0_MSGMEM_RAM_BASE:
    case CSL_MCU_MCAN1_MSGMEM_RAM_BASE:
        offsetAddr = &mcuMcanOffsetAddr;
        break;
#endif
#if defined(SOC_TPR12)
    case CSL_MSS_MCANA_MSG_RAM_U_BASE:
    case CSL_MSS_MCANB_MSG_RAM_U_BASE:
        offsetAddr = &mcuMcanOffsetAddr;
        break;
#endif
#if defined(SOC_J721E) || defined(SOC_J7200)
    case CSL_MCAN0_MSGMEM_RAM_BASE:
    case CSL_MCAN1_MSGMEM_RAM_BASE:
    case CSL_MCAN2_MSGMEM_RAM_BASE:
    case CSL_MCAN3_MSGMEM_RAM_BASE:
    case CSL_MCAN4_MSGMEM_RAM_BASE:
    case CSL_MCAN5_MSGMEM_RAM_BASE:
    case CSL_MCAN6_MSGMEM_RAM_BASE:
    case CSL_MCAN7_MSGMEM_RAM_BASE:
    case CSL_MCAN8_MSGMEM_RAM_BASE:
    case CSL_MCAN9_MSGMEM_RAM_BASE:
    case CSL_MCAN10_MSGMEM_RAM_BASE:
    case CSL_MCAN11_MSGMEM_RAM_BASE:
    case CSL_MCAN12_MSGMEM_RAM_BASE:
    case CSL_MCAN13_MSGMEM_RAM_BASE:
#if defined(SOC_J7200)
    case CSL_MCAN14_MSGMEM_RAM_BASE:
    case CSL_MCAN15_MSGMEM_RAM_BASE:
    case CSL_MCAN16_MSGMEM_RAM_BASE:
    case CSL_MCAN17_MSGMEM_RAM_BASE:
#endif /* #if defined (SOC_J7200) */
        offsetAddr = &mainMcanOffsetAddr;
        break;
#endif /* #if defined (SOC_J721E) || defined (SOC_J7200) */
    default:
        offsetAddr = NULL;
        break;
    }
    return offsetAddr;
}

static uint32_t MCAN_SsAddr(uint32_t baseAddr)
{
    int64_t mcanSsAddr = (uint64_t)NULL;
    const MCAN_OffsetAddr *offsetAddr = MCAN_getOffsetAddr(baseAddr);
    if (offsetAddr != NULL)
    {
        mcanSsAddr = (int64_t)baseAddr + offsetAddr->mcanSsOffset;
    }
    return ((uint32_t)mcanSsAddr);
}
#endif /*MCAN_DEBUG*/

/**
 * \brief   This function will configure MCAN module
 *
 * \param   index  [IN]  - MCAN index number
 *
 * \return  int8_t
 *             0   - in case of success
 *            -1   - in case of failure
 *
 */
int8_t mcanConfig(uint8_t mcanIndex,
                  MCAN_InitParams initParams,
                  MCAN_ConfigParams configParams,
                  MCAN_MsgRAMConfigParams msgRAMConfigParams,
                  MCAN_StdMsgIDFilterElement stdFiltelem,
                  MCAN_BitTimingParams bitTimes)
{
    appLogPrintf("MCAN: Config ...\n");
    uint32_t fdoe;
    uint32_t baseAddr;
    uint32_t regVal;
    MCAN_RevisionId revId;

    /* Set base address */
    baseAddr = gMcanDiagPortInfo[mcanIndex].mcanBaseAddr;

#if 0
    uint64_t i = 3000;
    while (i > 0)
    {
        i--;
        appLogWaitMsecs(100u);
    }
#endif
    //appLogWaitMsecs(90000u);

    appLogPrintf("MCAN: baseAddr = 0x%x\n", baseAddr);

    regVal = HW_RD_REG32(MCAN_SsAddr(baseAddr) + MCAN_MCANSS_PID);
    appLogPrintf("MCAN: baseAddr regVal = 0x%x\n", regVal);

    /* Get MCANSS Revision ID */
    MCAN_getRevisionId(baseAddr, &revId);

    appLogPrintf("MCANSS Revision ID:\n");
    appLogPrintf("scheme:0x%x\n", revId.scheme);
    appLogPrintf("Business Unit:0x%x\n", revId.bu);
    appLogPrintf("Module ID:0x%x\n", revId.modId);
    appLogPrintf("RTL Revision:0x%x\n", revId.rtlRev);
    appLogPrintf("Major Revision:0x%x\n", revId.major);
    appLogPrintf("Custom Revision:0x%x\n", revId.custom);
    appLogPrintf("Minor Revision:0x%x\n", revId.minor);

    /* Enable Auto wakeup */
    fdoe = MCAN_isFDOpEnable(baseAddr);
    if ((uint32_t)TRUE == fdoe)
    {
        appLogPrintf("CAN-FD operation is enabled through E-Fuse.\n");
    }
    else
    {
        appLogPrintf("CAN-FD operation is disabled through E-Fuse.\n");
    }
    /* wait for memory initialization to happen */
    while (FALSE == MCAN_isMemInitDone(baseAddr))
    {
    }

    /* Get endianess value */
    appLogPrintf("Endianess Value:0x%x\n", MCAN_getEndianVal(baseAddr));

    /* Put MCAN in SW initialization mode */
    MCAN_setOpMode(baseAddr, MCAN_OPERATION_MODE_SW_INIT);
    while (MCAN_OPERATION_MODE_SW_INIT != MCAN_getOpMode(baseAddr))
    {
    }

#if 1
    /* Initialize MCAN module */
    MCAN_init(baseAddr, &initParams);

    /* Configure MCAN module */
    MCAN_config(baseAddr, &configParams);

    /* Configure Bit timings */
    MCAN_setBitTime(baseAddr, &bitTimes);

    /* Set Extended ID Mask */
    MCAN_setExtIDAndMask(baseAddr, APP_MCAN_EXT_ID_AND_MASK);

    /* Configure Message RAM Sections */
    MCAN_msgRAMConfig(baseAddr, &msgRAMConfigParams);

    /* Configure Standard ID filter element */
    MCAN_addStdMsgIDFilter(baseAddr, 0U, &stdFiltelem);

    /* Take MCAN out of the SW initialization mode */
    MCAN_setOpMode(baseAddr, MCAN_OPERATION_MODE_NORMAL);
    while (MCAN_OPERATION_MODE_NORMAL != MCAN_getOpMode(baseAddr))
    {
    }
#endif
    appLogPrintf("MCAN: Config ... Done\n");

    return 0;
}

#if defined(MCAN_DIAG_INTR_ENABLE)
/**
 * \brief   This API will disable the TX and RX interrupts
 *
 * \param   baseAddr  [IN]  MCAN base address
 *
 */
static void BoardDiag_mcanTxIntDisable(uint32_t baseAddr)
{
    /* Disable Interrupts */
    MCAN_enableIntr(baseAddr, MCAN_INTR_MASK_ALL, (uint32_t)FALSE);
    MCAN_enableIntr(baseAddr,
                    MCAN_INTR_SRC_RES_ADDR_ACCESS, (uint32_t)FALSE);
    /* Select Interrupt Line */
    MCAN_selectIntrLine(baseAddr,
                        MCAN_INTR_MASK_ALL,
                        MCAN_INTR_LINE_NUM_0);
    /* Disable Interrupt Line */
    MCAN_enableIntrLine(baseAddr,
                        MCAN_INTR_LINE_NUM_0,
                        0U);
}

/**
 * \brief   This API will disable the RX interrupts
 *
 * \param   baseAddr  [IN]  MCAN base address
 *
 */
static void BoardDiag_mcanRxIntDisable(uint32_t baseAddr)
{
    /* Disable Interrupts */
    MCAN_enableIntr(baseAddr, MCAN_INTR_MASK_ALL, (uint32_t)FALSE);
    MCAN_enableIntr(baseAddr,
                    MCAN_INTR_SRC_RES_ADDR_ACCESS, (uint32_t)FALSE);
    /* Select Interrupt Line */
    MCAN_selectIntrLine(baseAddr,
                        MCAN_INTR_MASK_ALL,
                        MCAN_INTR_LINE_NUM_1);
    /* Disable Interrupt Line */
    MCAN_enableIntrLine(baseAddr,
                        MCAN_INTR_LINE_NUM_1,
                        0U);
}
/**
 * \brief   This API will enables the RX interrupts
 *
 * \param   baseAddr  [IN]  MCAN base address
 *
 */
static void BoardDiag_mcanRxIntEnable(uint32_t baseAddr)
{
    /* Enable Interrupts */
    MCAN_enableIntr(baseAddr, MCAN_INTR_MASK_ALL, (uint32_t)TRUE);
    MCAN_enableIntr(baseAddr,
                    MCAN_INTR_SRC_RES_ADDR_ACCESS, (uint32_t)FALSE);
    /* Select Interrupt Line */
    MCAN_selectIntrLine(baseAddr,
                        MCAN_INTR_MASK_ALL,
                        MCAN_INTR_LINE_NUM_1);
    /* Enable Interrupt Line */
    MCAN_enableIntrLine(baseAddr,
                        MCAN_INTR_LINE_NUM_1,
                        1U);
}

/**
 * \brief   This API will enables the TX interrupts
 *
 * \param   baseAddr  [IN]  MCAN base address
 *
 */
static int32_t BoardDiag_mcanTxIntEnable(uint32_t baseAddr)
{
    int32_t status = 0;
    MCAN_enableIntr(baseAddr, MCAN_INTR_MASK_ALL, (uint32_t)TRUE);
    MCAN_enableIntr(baseAddr,
                    MCAN_INTR_SRC_RES_ADDR_ACCESS, (uint32_t)FALSE);
    /* Select Interrupt Line */
    MCAN_selectIntrLine(baseAddr,
                        MCAN_INTR_MASK_ALL,
                        MCAN_INTR_LINE_NUM_0);
    /* Enable Interrupt Line */
    MCAN_enableIntrLine(baseAddr,
                        MCAN_INTR_LINE_NUM_0,
                        1U);
    /* Enable Transmission interrupt */
    status = MCAN_txBufTransIntrEnable(baseAddr,
                                       1U,
                                       (uint32_t)TRUE);
    return status;
}

/**
 * \brief   This is Interrupt Service Routine for MCAN Tx interrupt.
 *
 * \param   handle [IN/OUT] mcasp info structure
 *
 */
static void BoardDiag_mcanTxIntrISR(void *handle)
{
    uint32_t intrStatus;
    uint32_t baseAddrs;
    BoardDiag_McanPortInfo_t *intrInfo;

    intrInfo = (BoardDiag_McanPortInfo_t *)handle;
    baseAddrs = intrInfo->mcanBaseAddr;

    intrStatus = MCAN_getIntrStatus(baseAddrs);
    MCAN_clearIntrStatus(baseAddrs, intrStatus);
    if (MCAN_INTR_SRC_TRANS_COMPLETE ==
        (intrStatus & MCAN_INTR_SRC_TRANS_COMPLETE))
    {
        gMcanIsrIntr0Flag = 0U;
    }
}

/**
 * \brief   This is Interrupt Service Routine for MCAN Rx interrupt.
 *
 * \param   handle [IN/OUT] mcasp info structure
 *
 */
static void BoardDiag_mcanRxIntrISR(void *handle)
{
    uint32_t intrStatus;
    uint32_t baseAddrs;
    BoardDiag_McanPortInfo_t *intrInfo;

    intrInfo = (BoardDiag_McanPortInfo_t *)handle;
    baseAddrs = intrInfo->mcanBaseAddr;

    intrStatus = MCAN_getIntrStatus(baseAddrs);
    MCAN_clearIntrStatus(baseAddrs, intrStatus);
    if (MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG ==
        (intrStatus & MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG))
    {
        gMcanIsrIntr1Flag = 0U;
    }
}

/**
 * \brief   This function will configure MCAN Tx interrupts
 *
 * \param   index  [IN]  - MCAN index number
 *
 */
static void BoardDiag_mcanTxIntrConfig(uint32_t index)
{
#if !defined(SOC_AM64X)
#if defined(__aarch64__)
    Intc_Init(0);

    /* Enable CPU Interrupts and register ISR - MCAN Intr0 */
    Intc_IntRegister(gMcanDiagPortInfo[index].mcanTxIntNum,
                     (IntrFuncPtr)BoardDiag_mcanTxIntrISR, (void *)(&gMcanDiagPortInfo[index]));
    Intc_IntPrioritySet(gMcanDiagPortInfo[index].mcanTxIntNum, 1U, 0U);
    Intc_SystemEnable(gMcanDiagPortInfo[index].mcanTxIntNum);
    appLogPrintf("Tx Interrupt Configuration done.\n");
#endif
#else
#if !defined(__aarch64__)
    Intc_Init(0);

    /* Enable CPU Interrupts and register ISR - MCAN Intr0 */
    Intc_IntRegister(gMcanDiagPortInfo[index].mcanTxIntNum,
                     (IntrFuncPtr)BoardDiag_mcanTxIntrISR, (void *)(&gmcanDiagportInfo[index]));
    Intc_IntPrioritySet(gMcanDiagPortInfo[index].mcanTxIntNum, 1U, 0U);
    Intc_SystemEnable(gMcanDiagPortInfo[index].mcanTxIntNum);
    appLogPrintf("Tx Interrupt Configuration done.\n");
#endif
#endif
}

/**
 * \brief   This function will configure MCAN Rx interrupts
 *
 * \param   index  [IN]  - MCAN index number
 *
 */
static void BoardDiag_mcanRxIntrConfig(uint32_t index)
{
#if !defined(SOC_AM64X)
#if defined(__aarch64__)
    Intc_Init(0);

    /* Enable CPU Interrupts and register ISR - MCAN Intr0 */
    Intc_IntRegister(gMcanDiagPortInfo[index].mcanRxIntNum,
                     (IntrFuncPtr)BoardDiag_mcanRxIntrISR, (void *)(&gMcanDiagPortInfo[index]));
    Intc_IntPrioritySet(gMcanDiagPortInfo[index].mcanRxIntNum, 1U, 0U);
    Intc_SystemEnable(gMcanDiagPortInfo[index].mcanRxIntNum);
    appLogPrintf("Rx Interrupt Configuration done.\n");
#endif
#else
#if !defined(__aarch64__)
    Intc_Init(0);

    /* Enable CPU Interrupts and register ISR - MCAN Intr0 */
    Intc_IntRegister(gMcanDiagPortInfo[index].mcanRxIntNum,
                     (IntrFuncPtr)BoardDiag_mcanRxIntrISR, (void *)(&gmcanDiagportInfo[index]));
    Intc_IntPrioritySet(gMcanDiagPortInfo[index].mcanRxIntNum, 1U, 0U);
    Intc_SystemEnable(gMcanDiagPortInfo[index].mcanRxIntNum);
    appLogPrintf("Rx Interrupt Configuration done.\n");
#endif
#endif
}

#if defined(MCAN_DIAG_TS_INT_ENABLE)
/**
 * \brief   This is Interrupt Service Routine for MCAN TimeStamp interrupt.
 *
 * \param   handle [IN/OUT] mcasp info structure
 *
 */
static void BoardDiag_mcanTsIntrISR(void *handle)
{
    uint32_t baseAddrs;
    BoardDiag_McanPortInfo_t *intrInfo;

    intrInfo = (BoardDiag_McanPortInfo_t *)handle;
    baseAddrs = intrInfo->mcanBaseAddr;
    if (MCAN_extTSIsIntrEnable(baseAddrs) == (uint32_t)TRUE)
    {
        appLogPrintf("MCAN Time Stamp overflow happened.\n");
    }

    MCAN_extTSClearRawStatus(baseAddrs);
    MCAN_extTSWriteEOI(baseAddrs);
}

/**
 * \brief   This function will configure MCAN Rx interrupts
 *
 * \param   index  [IN]  - MCAN index number
 *
 */
static void BoardDiag_mcanTsIntrConfig(uint32_t index)
{
#if !defined(SOC_AM64X)
#if defined(__aarch64__)
    Intc_Init(0);

    /* Enable CPU Interrupts and register ISR - MCAN Intr0 */
    Intc_IntRegister(gMcanDiagPortInfo[index].mcanTsIntNum,
                     (IntrFuncPtr)BoardDiag_mcanTsIntrISR, (void *)(&gMcanDiagPortInfo[index]));
    Intc_IntPrioritySet(gMcanDiagPortInfo[index].mcanTsIntNum, 1U, 0U);
    Intc_SystemEnable(gMcanDiagPortInfo[index].mcanTsIntNum);
    appLogPrintf("Tx Interrupt Configuration done.\n");
#endif
#else
#if !defined(__aarch64__)
    Intc_Init(0);

    /* Enable CPU Interrupts and register ISR - MCAN Intr0 */
    Intc_IntRegister(gMcanDiagPortInfo[index].mcanTsIntNum,
                     (IntrFuncPtr)BoardDiag_mcanTsIntrISR, (void *)(&gmcanDiagportInfo[index]));
    Intc_IntPrioritySet(gMcanDiagPortInfo[index].mcanTsIntNum, 1U, 0U);
    Intc_SystemEnable(gMcanDiagPortInfo[index].mcanTsIntNum);
    appLogPrintf("Tx Interrupt Configuration done.\n");
#endif
#endif
}
#endif /* #if defined(MCAN_DIAG_TS_INT_ENABLE) */
#endif /* #if defined(MCAN_DIAG_INTR_ENABLE) */

#if defined(BOARD_DIAG_MCAN_DEBUG)
/**
 * \brief   This API will print MCAN Tx Msg.
 *
 */
static void BoardDiag_mcanPrintTxMsg(void)
{
    uint32_t loopCnt;

    appLogPrintf("\nMessage ID:0x%x\n", txMsg.id);

    appLogPrintf("\nMessage Remote Transmission Request:0x%x\n", txMsg.rtr);

    appLogPrintf("\nMessage Extended Frame ID(0:11Bit ID/1:29bit ID):0x%x\n",
                 txMsg.xtd);

    appLogPrintf("\nMessage Error State Indicator(0:Error Active/1:Error Passive):0x%x\n", txMsg.esi);

    appLogPrintf("\nMessage Data Length Code:0x%x\n", txMsg.dlc);

    appLogPrintf("\nMessage BRS:0x%x\n", txMsg.brs);

    appLogPrintf("\nMessage CAN FD format:0x%x\n", txMsg.fdf);

    appLogPrintf("\nMessage Store Tx Events:0x%x\n", txMsg.efc);

    appLogPrintf("\nMessage Marker:0x%x\n", txMsg.mm);

    for (loopCnt = 0U; loopCnt < txMsg.dlc; loopCnt++)
    {
        appLogPrintf("\nMessage DataByte%d:0x%x\n", loopCnt, txMsg.data[loopCnt]);
    }
}

/**
 * \brief   This API will print MCAN Rx Msg.
 *
 */
static void BoardDiag_mcanPrintRxMsg(void)
{
    uint32_t loopCnt;

    appLogPrintf("\nReceived last message with following details:");

    appLogPrintf("\nMessage ID:0x%x\n", rxMsg.id);

    appLogPrintf("\nMessage Remote Transmission Request:0x%x\n", rxMsg.rtr);

    appLogPrintf("\nMessage Extended Frame ID(0:11Bit ID/1:29bit ID):0x%x\n",
                 rxMsg.xtd);

    appLogPrintf("\nMessage Error State Indicator(0:Error Active/1:Error Passive):0x%x\n", rxMsg.esi);

    appLogPrintf("\nMessage TimeStamp:0x%x\n", rxMsg.rxts);

    appLogPrintf("\nMessage Data Length Code:0x%x\n", rxMsg.dlc);

    appLogPrintf("\nMessage BRS:0x%x\n", rxMsg.brs);

    appLogPrintf("\nMessage CAN FD format:0x%x\n", rxMsg.fdf);

    appLogPrintf("\nMessage Filter Index:0x%x\n", rxMsg.fidx);

    appLogPrintf("\nMessage Accept Non-matching Frame:0x%x\n", rxMsg.anmf);

    for (loopCnt = 0U; loopCnt < rxMsg.dlc; loopCnt++)
    {
        appLogPrintf("\nMessage DataByte%d:0x%x\n", loopCnt, rxMsg.data[loopCnt]);
    }
}
#endif /* #if defined(BOARD_DIAG_MCAN_DEBUG) */

/**
 * \brief   This API will load the data to the message ram and checking
 *          the error status
 *
 * \param   instance  [IN]  - MCAN instance number
 *
 * \return  int8_t
 *             0   - in case of success
 *            -1   - in case of failure
 *
 */
int8_t mcanTx(uint8_t instance, MCAN_TxBufElement *pTxMsg)
{
    int8_t configStatus = 0;
    uint32_t baseAddr;
    MCAN_ProtocolStatus protStatus;

    /* Set base address */
    baseAddr = gMcanDiagPortInfo[instance].mcanBaseAddr;

#if defined(MCAN_DIAG_INTR_ENABLE)
    BoardDiag_mcanTxIntrConfig(instance);
    configStatus = BoardDiag_mcanTxIntEnable(baseAddr);
#endif

    /* Write message to Msg RAM */
    MCAN_writeMsgRam(baseAddr,
                     MCAN_MEM_TYPE_BUF,
                     APP_MCAN_TX_BUF_NUM,
                     pTxMsg);

    /* Add request for transmission */
    configStatus += MCAN_txBufAddReq(baseAddr, APP_MCAN_TX_BUF_NUM);
    if (configStatus != 0)
    {
        appLogPrintf("\nError in Adding Transmission Request...\n");
        return -1;
    }

#if defined(MCAN_DIAG_INTR_ENABLE)
    while (gMcanIsrIntr0Flag)
    {
    }
    gMcanIsrIntr0Flag = 1U;
#else
    /* Waiting for Transmission Complete */
    while (((MCAN_getTxBufReqPend(baseAddr) >>
             APP_MCAN_TX_BUF_NUM) &
            0x1) == 0x1)
        ;
#endif

    MCAN_getProtocolStatus(baseAddr, &protStatus);
    /* Checking for Errors */
    if (((MCAN_ERR_CODE_NO_ERROR == protStatus.lastErrCode) ||
         (MCAN_ERR_CODE_NO_CHANGE == protStatus.lastErrCode)) &&
        ((MCAN_ERR_CODE_NO_ERROR == protStatus.dlec) ||
         (MCAN_ERR_CODE_NO_CHANGE == protStatus.dlec)) &&
        (0U == protStatus.pxe))
    {
        appLogPrintf("\nMessage successfully transferred with payload Bytes:0x%x\n", pTxMsg->dlc);
    }
    else
    {
        appLogPrintf("\nError in transmission with payload Bytes:0x%x\n", pTxMsg->dlc);
        configStatus = -1;
    }

    return configStatus;
}

/**
 * \brief   This API will receive the data and compares with the transmit data
 *
 * \param   instance  [IN]  - MCAN instance number
 *
 * \return  int8_t
 *             0   - in case of success
 *            -1   - in case of failure
 *
 */
int8_t mcanRx(uint8_t index, MCAN_RxBufElement *pRxMsg)
{
    //uint32_t chkCnt = 0U;
    uint32_t errFlag = 0U;
    uint32_t baseAddr;
    int8_t testStatus = 0;
    MCAN_RxNewDataStatus newDataStatus;
    MCAN_ErrCntStatus errCounter;

    /* Set base address */
    baseAddr = gMcanDiagPortInfo[index].mcanBaseAddr;

#if defined(MCAN_DIAG_INTR_ENABLE)
    BoardDiag_mcanRxIntrConfig(index);
    BoardDiag_mcanRxIntEnable(baseAddr);
#endif

#if defined(MCAN_DIAG_INTR_ENABLE)
    while (gMcanIsrIntr1Flag)
    {
    }
    gMcanIsrIntr1Flag = 1U;
#else
    /* Waiting for Transmission Complete */
    while (MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG !=
           (MCAN_getIntrStatus(baseAddr) &
            MCAN_INTR_SRC_DEDICATED_RX_BUFF_MSG))
        ;

#endif

    /* Checking for Errors */
    MCAN_getErrCounters(baseAddr, &errCounter);
    if ((0U == errCounter.recErrCnt) &&
        (0U == errCounter.canErrLogCnt))
    {
        MCAN_getNewDataStatus(baseAddr, &newDataStatus);
        MCAN_clearNewDataStatus(baseAddr, &newDataStatus);
        MCAN_readMsgRam(baseAddr,
                        MCAN_MEM_TYPE_BUF,
                        0U,
                        0U,
                        pRxMsg);

        errFlag = 0U;

        if (0U == errFlag)
        {
            appLogPrintf("\nMessage successfully received with payload Bytes:0x%x\n", pRxMsg->dlc);
        }
        else
        {
            appLogPrintf("\nWrong data received in message with payload Bytes:0x%x\n", pRxMsg->dlc);
            testStatus = -1;
        }
    }
    else
    {
        appLogPrintf("\nError in reception with payload Bytes:0x%x\n", pRxMsg->dlc);
        testStatus = -1;
    }

#if defined(BOARD_DIAG_MCAN_DEBUG)
    BoardDiag_mcanPrintRxMsg();
#endif

    return testStatus;
}

/**
 * \brief   This API Initializes the GPIO module
 *
 * \param    gpioBaseAddrs [IN]  GPIO base address to configure
 * \param    port          [IN]  GPIO Port number
 *
 */
static void mcanGpioConfig(uint32_t gpioBaseAddrs, uint32_t port)
{
    GPIO_v0_HwAttrs gpioCfg;
    GPIO_socGetInitCfg(port, &gpioCfg);
    gpioCfg.baseAddr = gpioBaseAddrs;
    GPIO_socSetInitCfg(port, &gpioCfg);
    /* GPIO initialization */
    GPIO_init();
}

#ifdef PRODUCT
static void gpioPinmuxConfig(uint32_t baseAddr, uint32_t offset, uint32_t value)
{
    volatile uint32_t *tmp = (uint32_t *)(baseAddr + offset);
    *tmp = value;
}
#endif

/**
 * \brief  This function enable MCAN by set STB signal
 *
 * \return  void
 *
 */

void mcanEnable(uint8_t mcanIndex)
{
    appLogPrintf("MCAN: Enable ...\n");
#ifdef PRODUCT
    mcanGpioConfig(CSL_WKUP_GPIO0_BASE, 0);

    switch (mcanIndex)
    {
    case MCU_MCAN0_INDEX:
        gpioPinmuxConfig(0x43000000UL, 0x1C0DCUL, 0x00050007);
        GPIO_write(0, 0); /* MCU_CAN0_STB */
        break;

    case MCU_MCAN1_INDEX:
        gpioPinmuxConfig(0x43000000UL, 0x1C0D8UL, 0x00050007);
        GPIO_write(1, 0); /* MCU_CAN1_STB */
        break;

    default:
        break;
    }
#else
    mcanGpioConfig(CSL_WKUP_GPIO0_BASE, 0);
    /* Enable MCU CAN transceivers by setting the STB pins */
    GPIO_write(0, 1); /* MCU_CAN0_STB */
    GPIO_write(1, 0); /* MCU_CAN1_STB */
    /* MCU_MCAN0_EN */
    GPIO_write(2, 1); /* WKUP_GPIO0_0 */

    appLogPrintf("MCAN: Enable ... Done\n");
#endif
}

/**
 * \brief  This function executes MCAN Diagnostic test
 *
 * \return  int8_t
 *           0  - in case of success
 *          -1  - in case of failure
 *
 */
int32_t canTest(void)
{
    int8_t ret = 0;

    MCAN_TxBufElement txMsg;
    MCAN_RxBufElement rxMsg;

    mcanEnable(MCU_MCAN0_INDEX);
    mcanEnable(MCU_MCAN1_INDEX);

    MCAN_InitParams initParams;
    MCAN_ConfigParams configParams;
    MCAN_MsgRAMConfigParams msgRAMConfigParams;
    MCAN_StdMsgIDFilterElement stdFiltelem;
    MCAN_BitTimingParams bitTimes;

    /* Initialize MCAN Init params */
    initParams.fdMode = 0x1U;
    initParams.brsEnable = 0x1U;
    initParams.txpEnable = 0x0U;
    initParams.efbi = 0x0U;
    initParams.pxhddisable = 0x0U;
    initParams.darEnable = 0x1U;
    initParams.wkupReqEnable = 0x1U;
    initParams.autoWkupEnable = 0x1U;
    initParams.emulationEnable = 0x1U;
    initParams.emulationFAck = 0x0U;
    initParams.clkStopFAck = 0x0U;
    initParams.wdcPreload = 0xFFU;
    initParams.tdcEnable = 0x1U;
    initParams.tdcConfig.tdcf = 0xAU;
    initParams.tdcConfig.tdco = 0x6U;

    /* Initialize MCAN Config params */
    configParams.monEnable = 0x0U;
    configParams.asmEnable = 0x0U;
    configParams.tsPrescalar = 0xFU;
    configParams.tsSelect = 0x0U;
    configParams.timeoutSelect = MCAN_TIMEOUT_SELECT_CONT;
    configParams.timeoutPreload = 0xFFFFU;
    configParams.timeoutCntEnable = 0x0U;
    configParams.filterConfig.rrfs = 0x1U;
    configParams.filterConfig.rrfe = 0x1U;
    configParams.filterConfig.anfe = 0x1U;
    configParams.filterConfig.anfs = 0x1U;

    /* Initialize Message RAM Sections Configuration Parameters */
    msgRAMConfigParams.flssa = APP_MCAN_STD_ID_FILT_START_ADDR;
    msgRAMConfigParams.lss = APP_MCAN_STD_ID_FILTER_NUM;
    msgRAMConfigParams.flesa = APP_MCAN_EXT_ID_FILT_START_ADDR;
    msgRAMConfigParams.lse = APP_MCAN_EXT_ID_FILTER_NUM;

    msgRAMConfigParams.txStartAddr = APP_MCAN_TX_BUFF_START_ADDR;
    msgRAMConfigParams.txBufNum = APP_MCAN_TX_BUFF_SIZE;
    msgRAMConfigParams.txFIFOSize = 0U;
    msgRAMConfigParams.txBufMode = 0U;
    msgRAMConfigParams.txBufElemSize = MCAN_ELEM_SIZE_64BYTES;
    msgRAMConfigParams.txEventFIFOStartAddr = APP_MCAN_TX_EVENT_START_ADDR;
    msgRAMConfigParams.txEventFIFOSize = APP_MCAN_TX_BUFF_SIZE;
    msgRAMConfigParams.txEventFIFOWaterMark = 3U;

    msgRAMConfigParams.rxFIFO0startAddr = APP_MCAN_FIFO_0_START_ADDR;
    msgRAMConfigParams.rxFIFO0size = APP_MCAN_FIFO_0_NUM;
    msgRAMConfigParams.rxFIFO0waterMark = 3U;
    msgRAMConfigParams.rxFIFO0OpMode = 0U;
    msgRAMConfigParams.rxFIFO1startAddr = APP_MCAN_FIFO_1_START_ADDR;
    msgRAMConfigParams.rxFIFO1size = APP_MCAN_FIFO_1_NUM;
    msgRAMConfigParams.rxFIFO1waterMark = 3U;
    msgRAMConfigParams.rxFIFO1OpMode = 0U;
    msgRAMConfigParams.rxBufStartAddr = APP_MCAN_RX_BUFF_START_ADDR;
    msgRAMConfigParams.rxBufElemSize = MCAN_ELEM_SIZE_64BYTES;
    msgRAMConfigParams.rxFIFO0ElemSize = MCAN_ELEM_SIZE_64BYTES;
    msgRAMConfigParams.rxFIFO1ElemSize = MCAN_ELEM_SIZE_64BYTES;

    /* Initialize Tx Buffer Config params */
    stdFiltelem.sfid2 = 0x0U;
    stdFiltelem.sfid1 = 0x4U;
    stdFiltelem.sfec = 0x7U;
    stdFiltelem.sft = 0x0U;

    /* Initialize bit timings
     * Configuring 1Mbps and 5Mbps as nominal and data bit-rate respectively */
    bitTimes.nomRatePrescalar = 0x7U;
    bitTimes.nomTimeSeg1 = 0x5U;
    bitTimes.nomTimeSeg2 = 0x2U;
    bitTimes.nomSynchJumpWidth = 0x0U;
    bitTimes.dataRatePrescalar = 0x1U;
    bitTimes.dataTimeSeg1 = 0x3U;
    bitTimes.dataTimeSeg2 = 0x2U;
    bitTimes.dataSynchJumpWidth = 0x0U;

#if 0
    uint64_t i = 3000;
    while (i > 0)
    {
        i--;
        appLogWaitMsecs(100u);
    }
#endif
    //appLogWaitMsecs(60000u);

    ret = mcanConfig(MCU_MCAN0_INDEX, initParams, configParams,
                     msgRAMConfigParams, stdFiltelem, bitTimes);
    if (ret == 0)
    {
        appLogPrintf("Successfully configured MCAN%d\n", MCU_MCAN0_INDEX);
    }
    ret = mcanConfig(MCU_MCAN1_INDEX, initParams, configParams,
                     msgRAMConfigParams, stdFiltelem, bitTimes);
    if (ret == 0)
    {
        appLogPrintf("Successfully configured MCAN%d\n", MCU_MCAN1_INDEX);
    }
#if 1
    /* Initialize message to transmit */
    txMsg.id = (uint32_t)((uint32_t)(0x4U) << 18U);
    txMsg.rtr = 0U;
    txMsg.xtd = 0U;
    txMsg.esi = 0U;
    txMsg.dlc = 0xFU;
    txMsg.brs = 1U;
    txMsg.fdf = 1U;
    txMsg.efc = 1U;
    txMsg.mm = 0xAAU;

    //appLogPrintf("\nSending Packet - %d\n", (index + 1));
    /* Fill the Tx buffer with random data */
    BoardDiag_genPattern(txMsg.data, MCAN_MAX_PAYLOAD_BYTES,
                         BOARD_DIAG_TEST_PATTERN_AA_55);

    /* Transmiting port */
    ret = mcanTx(MCU_MCAN0_INDEX, &txMsg);
    if (ret != 0)
    {
        appLogPrintf("Failed to transmit data on port%d\n", 0);
        return (-1);
    }

    /* Receiving port*/
    ret = mcanRx(MCU_MCAN1_INDEX, &rxMsg);
    if (ret != 0)
    {
        appLogPrintf("Failed to receive data on port%d", 1);
        return (-1);
    }
#endif
    return ret;
}