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DDR3 leveling procedure (code or algorithm)

Other Parts Discussed in Thread: AM3352, AM3358

Hi All,

I'm bringing up a board based on the AM3352, using a DDR3. The board is using a custom boot loader, and my dev system is entirely Linux. The DDR3 appears to be working reliably at 303MHz even though I've not yet worked out the optimum PHY timing values. Regardless, I won't feel comfortable until I've gone through that step.

To that end, I found the web page "AM335x DDR PHY register configuration for DDR3 using Software Leveling", however the procedure given there involves CCS (which I'm currently not using). For my development process, it would be simpler if I could just grab the source code which performs this step, and build it in my environment. Does TI make this code available? If not, is there a detailed (register level) description of the algorithm it performs? I'm happy to write the code myself, but none of the doc I've found so far gives me quite enough detail to do that.

Thanks.