About GPMC address line behavior

g.f.

Hi,

I have a question about AM335x GPMC address Line.

I'm using Multiplexed Address Data 16bit mode,
and setting BASEADDRESS and MASKFIELD bit field of GPMC_CONFIG7_0 register
as follow:

BASEADDRESS : 0x1E (which means 0x1E00_0000)
MASKFIELD : 0xE (which means CS0 size = 32MByte)

If I access to address 0x1E00_0000,
I guess 'Low(zero)' will be output from all address line.
But when I checked by using oscilloscope, upper address line(A26, A25)of GPMC
are outputting 'High(one)' and other are Low. Is this behavior specification of GPMC?

We need the information about this behavior, so please help.

best regards,
g.f.

over 12 years ago

0 Biser Gatchev-XID over 12 years ago

TI__Guru**** 393215 points

Hi g.f,

In Multiplexed Address Data 16-bit mode the lowest address bit that's output is A1, not A0 (see Note 1 below Table 7-5 in AM335X TRM, Rev.H).

0 g.f. over 12 years ago in reply to Biser Gatchev-XID

Guru 15520 points

Hi Biser,

Thank you for the reply.

Yes, I understand that lowest address pin is A1, not A0.
Sorry, my explanation was not good.

If setting BASEADDRESS to 0x1E00_0000,
this address will correspond to begining of external memory address 0x0000_0000.
GPMC address space external memory
0x1E00_0000 ------ 0x0000_0000

So, as I mention above, if ARM core try to access GPMC address space 0x1E00_0000,
I guess all address pin will output "Low" level because the correspond address is zero.
But when I check the upper adrress pin A26(GPMC_A11 pin: set to pinmux mode4) and
A25(GPMC_10 pin : set to pinmux mode0), it outputs "High" level.
What I meant is, the output address is not 0x0000_0000 but 0x0600_0000.

best regards,
g.f.

0 Biser Gatchev-XID over 12 years ago in reply to g.f.

TI__Guru**** 393215 points

You have selected 32MB CS size, so the highest relevant 16-bit address would be 0x00FF_FFFF. The higher addresses are not relevant in this use case.

0 g.f. over 12 years ago in reply to Biser Gatchev-XID

Guru 15520 points

Hi Biser,

Thank you for the reply.

I see. I understand that A26/A25 are not relevant.
So, the higher address will output unkown level in the case.
But this won't influence to the other CS space, because one CS will be enabled at a time.
Am I right?

best regards,
g.f.

0 Biser Gatchev-XID over 12 years ago in reply to g.f.

TI__Guru**** 393215 points

Yes, this is correct.

0 g.f. over 12 years ago in reply to Biser Gatchev-XID

Guru 15520 points

Thank you so much.

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About GPMC address line behavior