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AM3517 L3 interconnect In-band error

RY9983
Guru 10570 points

Other Parts Discussed in Thread: AM3517


Hello,
I am facing In-band error in the AM3517 L3 interconnect.
I would like to ask you about idea to avoid this error.

I understand our system has heavy load in the L3 interconnect.
But, if there are some ideas to avoid, I would like to try it.

One of my ideas are:
  - I would like to set L3_ICLK frequency faster to reduce L3 load.

Could you help me, please?
I appreciate trivial informations.

Best regards, RY

  • 0
    TI__Guru**** 393215 points
    What software is running on the board?
  • 0 in reply to Biser Gatchev-XID
    Guru 10570 points


    Biser-san,
    Thank you so much for your response.

    The AM35x system performs video capture and video display simultaneously.
      VPFE 16-bit@30fps, 800*600, YUV422
      DSS  24-bit@60fps, 1024*768, RGB888

    When it is following configuration, in-band error have never  occured.
      VPFE 16-bit@30fps, 640*480, YUV422
      DSS  24-bit@60fps, 800*600, RGB888

    The OS is linux, and CortexA8 accesses to DDR to analyse capture data.

    I think that In-band error occurs when load is too heavy in the L3 interconnect.

     - What is the maximum throuput of L3 interconnect?
     - Do you have some idea to avoid in-band error?

    If you need other information, please let me know.

    Best regards, RY

  • 0 in reply to RY9983
    TI__Guru**** 393215 points
    Hi RY,
     
    Answering this involves information that I don't have. I will escalate this to the factory team.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 90745 points

    RY, max CORE_CLK is 333MHz (L3=166MHz).  You may want to ensure you are running this at the max frequency.  You can output this clock (with divide-by-2) on sys_clkout2.

    I'm not sure of the architecture of your data flow.  You may want to experiment with different arbitration schemes or priorities if you have DMAs setup to move data.  Do you have DMAs setup?

      Regards,

    James

  • 0 in reply to JJD
    Guru 10570 points

    Biser-san, James-san,
    Thank you so much for your advise.
    I would like to check DMAs setup .
    Best regards, RY

  • 0 in reply to RY9983
    Guru 10570 points

    Biser-san, James-san,

    Thank you for your support.
    Since VPFE or DSS flickers are not allowed on our system,
    I would like to set VPFE and DSS priority higher than CPU and other peripheral accesses.
    Can I set this by register settings? (like bus priority setting of IA and TA)

    Best regards, RY 

  • 0 in reply to RY9983
    Guru 10570 points

    James-san,

    I have been looking for the trick on the system.
    First, I would like to answer about your question.

    > I'm not sure of the architecture of your data flow.

    I could be reproduce the issue on my simple application.
    The issue occurs when the following processes operate simultaneously:

     a) VPFE captures video data to DDR. (16-bit@30fps, 800*600, YUV422)
     b) DSS  displays out data from DDR. (24-bit@60fps, 1024*768, RGB888)
     c) I allocate 1MByte memory on linux application. And, I read and write repeatedly.


    > Do you have DMAs setup?

    No, I have not used DMAs except for VPFE and DSS operations.

     

    My consideration is:
     - The band width of L3 interconnect is maximum 1328Mbyte/sec. (64bit@166MHz)
     - The band width of VPFE is calculated as 28.8Mbyte/sec. (800x600 x30fps x2byte)
     - The band width of DSS  is calculated as 141.6Mbyte/sec. (1024x768 x60fps x3byte)

    Since total band width of VPFE and DSS is 170Mbyte/sec, it is about 13% of all L3 band width.
    I think there is enough throughput.
      

    Question)
    I would like to clarify whether it is the limit band width for L3 interconnect on AM3517 spec.
    Do you think about it ?

    Best regards, RY