Automatic leveling and full leveling on C6654

OC,

We apologize for the confusion and are working to get the GEL updated in a future release.

For the correct sequence, you will need to add the following to your GEL file:

#define DDR3_CONFIG_REG_52   (*(unsigned int*)(CHIP_LEVEL_REG + 0x04D4))
#define DDR3_CONFIG_REG_53   (*(unsigned int*)(CHIP_LEVEL_REG + 0x04D8))
#define DDR3_CONFIG_REG_54   (*(unsigned int*)(CHIP_LEVEL_REG + 0x04DC))
#define DDR3_CONFIG_REG_55   (*(unsigned int*)(CHIP_LEVEL_REG + 0x04E0))
#define DDR3_CONFIG_REG_60   (*(unsigned int*)(CHIP_LEVEL_REG + 0x04F4))

Replace the write to DDR3_CONFIG_REG_23 with the following to enable Partial Automatic Leveling.

 DDR3_CONFIG_REG_52 |= 0x00000200;
 DDR3_CONFIG_REG_53 |= 0x00000200;
 DDR3_CONFIG_REG_54 |= 0x00000200;
 DDR3_CONFIG_REG_55 |= 0x00000200;
 DDR3_CONFIG_REG_60 |= 0x00000200;

The GEL file also initializes the wrong INIT_RATIO registers. Please see the correct registers below:

 DATA0_WRLVL_INIT_RATIO = 0x2C;
 DATA1_WRLVL_INIT_RATIO = 0x2C;
 DATA2_WRLVL_INIT_RATIO = 0x3A;
 DATA3_WRLVL_INIT_RATIO = 0x33;
 DATA8_WRLVL_INIT_RATIO = 0x1C;
 
 DATA0_GTLVL_INIT_RATIO = 0xA4;
 DATA1_GTLVL_INIT_RATIO = 0xA4;
 DATA2_GTLVL_INIT_RATIO = 0xB1;
 DATA3_GTLVL_INIT_RATIO = 0xB7;
 DATA8_GTLVL_INIT_RATIO = 0x98;

Yes you have to enable full leveling before you trigger it.

Full v/s automatic leveling:

I think there is some confusion when you look at the DDR3 Users guide and the DDR3 initialization app note. The correct terminology is "full automatic leveling" or "partial automatic leveling". The former does not use a fixed read data eye. The latter uses a fixed read data eye. We recommend using partial automatic leveling for best resutls. It is also the most widely used solution by our customers.