Results getting corrupted on my multicore project

Umesha M Y

Other Parts Discussed in Thread: SYSBIOS

Can anyone tell me why my multicore project's results are getting corrupted??

Project description:

My project which has several FFTs and IFFT (2K fft and ifft) computations and some mathematical operations.

I started my project running on one core and found working fine and got the best results( Without sys-bios ). Then I made the same project to work on multicore (on Evaluation board) and found successfully on all cores(8 c6678 cores) independently and got the again best(same) results on all cores independently. I used shared memory, on board 4MB and respective cores's L2SRAM(512K) to achieve this results ( Without sys-bios ).

Problem:

when I tried to use respective cores's L2SRAM(512K) my projects on the cores were hanging indefinitely...

Can anyone tell me why it is so?

Please tell me how to solve these issues...

looking forward for the kind reply...

over 10 years ago

0 Raja over 10 years ago

TI__Guru* 81335 points

Hi Umesha,

Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

When I run my project on 3rd and on others cores my results are getting corrupted. I used some of the shared memory (around 2MB) and DDR3 memory and I could not use respective cores's L2SRAM(512K) at all??.

How the memory sections are partitioned in your project using SYS/BIOS (.cfg) or linker command file (.cmd)?

Are you loading the same .out file on all cores or different?

I recommend you to post this query on TI-RTOS(sys/bios) forum with above information and share the .cfg or .cmd file for review.

Here is the link to TI-RTOS forum:

I will also check to provide some suggestions to solve the issue. Thank you.

0 Umesha M Y over 10 years ago in reply to Raja

Prodigy 60 points

Thank you sir for the reply...

Same question (little edited):

Can anyone tell me why my multicore project's results are getting corrupted??

Project description:

My project which has several FFTs and IFFT (2K fft and ifft) computations and some mathematical operations.

Working:

I started my project running on one core and found working fine and got the best results( Without sys-bios ). Then I made the same project to work on multicore (on Evaluation board and Commagility's 4C6678 board also) and found successfully on all cores(8 c6678 cores) independently and got the again best(same) results on all cores independently. I used shared memory, on board 4MB and respective cores's L2SRAM(512K) to achieve this results ( Without sys-bios ).

Problem:

I wanted to achieve the same above project's results with sys-bios environment. In this I could successfully make base multicore programming project using IPC (Message Q topology) master and slave fashion and I could add my project to this base multicore programming project. The problem is My project runs sucessfuly on all 8 cores on some LIMITATION (512 FFT and 16 TIMES (512*16 FFT) and got the best results same as above:). When I run my project on all cores results are getting corrupted(>512 FFT and 16 TIMES (>512FFT*16 buffer). That is 1024FFT (1024FFT*16 buffer) and 2048FFT (2048FFT*16 buffer) on all cores results are getting corrupted also I am using some of the shared memory (around 2MB) and DDR3 memory( some times all DDR3 memory (enclosed .cmd file) and I could not use respective cores's L2SRAM(512K) at all(with sysbios)??.

NOTE:

In my project all projects share the same source files and .cfg, linker and .cmd file to build and create respective .out files ! when I tried to use respective cores's L2SRAM(512K) my projects on the cores were hanging indefinitely...

Can anyone tell me why it is so? Please tell me how to solve these issues... looking forward for the kind reply...

Raja sir's questions on my same query:

How the memory sections are partitioned in your project using SYS/BIOS (.cfg) or linker command file (.cmd)?

sir pls enclosed all relevent files.. Pls go through these..

Are you loading the same .out file on all cores or different?

Different .out files

FILES:

1. ca_4c6678.cfg ->

/*use modules*/

var BIOS = xdc.useModule ("ti.sysbios.BIOS");

var Task = xdc.useModule ("ti.sysbios.knl.Task");

var ECM = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");

var C64_Hwi = xdc.useModule ("ti.sysbios.family.c64p.Hwi");

var Startup = xdc.useModule ("xdc.runtime.Startup");

var System = xdc.useModule ("xdc.runtime.System");

var Log = xdc.useModule ("xdc.runtime.Log");

var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');

var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');

var Cache = xdc.useModule('ti.sysbios.hal.Cache');

var CpIntc = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc');

ECM.eventGroupHwiNum[0] = 7;

ECM.eventGroupHwiNum[1] = 8;

ECM.eventGroupHwiNum[2] = 9;

ECM.eventGroupHwiNum[3] = 10;

/* Shared Memory base address and length */

var SHAREDMEM           = 0x0C000000;

var SHAREDMEMSIZE       = 0x00100000;

/*var SHAREDMEMSIZE     = 0x00200000;*/

/*  

*  Since this is a single-image example, we don't (at build-time) which  

*  processor we're building for.  We therefore supply 'null'  

*  as the local procName and allow IPC to set the local procId at runtime.

*/

var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');

MultiProc.setConfig(null, ["CORE0", "CORE1", "CORE2", "CORE3", "CORE4", "CORE5", "CORE6", "CORE7"]);

/*  

*  The SysStd System provider is a good one to use for debugging  

*  but does not have the best performance. Use xdc.runtime.SysMin

*  for better performance.

*/

var System   = xdc.useModule('xdc.runtime.System');

var SysStd   = xdc.useModule('xdc.runtime.SysStd');

System.SupportProxy = SysStd;

/* Modules explicitly used in the application */

var MessageQ    = xdc.useModule('ti.sdo.ipc.MessageQ');

var Ipc         = xdc.useModule('ti.sdo.ipc.Ipc');

var HeapBufMP   = xdc.useModule('ti.sdo.ipc.heaps.HeapBufMP');

var MultiProc   = xdc.useModule('ti.sdo.utils.MultiProc');

/* BIOS/XDC modules */

var BIOS        = xdc.useModule('ti.sysbios.BIOS');

BIOS.heapSize   = 0x8000;

var Task        = xdc.useModule('ti.sysbios.knl.Task');

/*var tsk0 = Task.create('&tsk0_func');*/

/*tsk0.instance.name = "tsk0";*/

/* Synchronize all processors (this will be done in Ipc_start) */

Ipc.procSync = Ipc.ProcSync_ALL;

/*  enable fast message Q */

/*var MessageQ = xdc.module('ti.sdo.ipc.MessageQ');

var Notify   = xdc.module('ti.sdo.ipc.Notify');

Notify.SetupProxy   = xdc.module('ti.sdo.ipc.family.c647x.NotifyCircSetup');

MessageQ.SetupTransportProxy = xdc.module('ti.sdo.ipc.transports.TransportShmNotifySetup');*/

/* data section */

//Program.sectMap[".internalMEM"]={runSegment: "L2SRAM_1"};

//Program.sectMap[".sharedMEM"]={runSegment: "MSMCSRAM_2"};

/*Program.sectMap[".internalL1SRAMMEM"]={runSegment: "L1SRAM"};*/

/*  

*  Need to define the shared region. The IPC modules use this

*  to make portable pointers. All processors need to add this

*  call with their base address of the shared memory region.

*  If the processor cannot access the memory, do not add it.

*/  

var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');

SharedRegion.setEntryMeta(0,

   { base: SHAREDMEM,  

     len:  SHAREDMEMSIZE,

     ownerProcId: 0,

     isValid: true,

     name: "MSMC RAM",

   });

/* Reset function initialize HW */

var Reset = xdc.useModule("xdc.runtime.Reset");

Reset.fxns[Reset.fxns.length++] = "&xapar_mtd_system_reset";

/*

*  @(#) ti.sdo.ipc.examples.multicore.evm667x; 1, 0, 0, 0,22; 1-20-2011 10:15:37; /db/vtree/library/trees/ipc/ipc.git/src/ ipc-f23

*/

2. ca_4c6678.cmd->

MEMORY

{

 #ifdef CORE0

     CORE0_L2_SRAM:   origin = 0x10800000 length = 0x00080000   /* 512kB CORE0 L2/SRAM */

     CORE0_L1P_SRAM:  origin = 0x10E00000 length = 0x00008000   /* 32kB CORE0 L1P/SRAM */

     CORE0_L1D_SRAM:  origin = 0x10F00000 length = 0x00008000   /* 32kB CORE0 L1D/SRAM */

     CORE0_DDR3:      origin = 0x80000000 length = 0x10000000   /* 256MB DDR3 SDRAM for CORE0 */

     CORE0_SHRAM:     origin = 0x0C2eef80 length = 0x00022210  /* <1MB Multicore shared Memmory */

 #endif

 #ifdef CORE1

     CORE1_L2_SRAM:   origin = 0x11800000 length = 0x00080000   /* 512kB CORE1 L2/SRAM */

     CORE1_L1P_SRAM:  origin = 0x11E00000 length = 0x00008000   /* 32kB CORE1 L1P/SRAM */

     CORE1_L1D_SRAM:  origin = 0x11F00000 length = 0x00008000   /* 32kB CORE1 L1D/SRAM */

     CORE1_DDR3:      origin = 0x90000000 length = 0x10000000   /* 256MB DDR3 SDRAM for CORE0 */

     CORE1_SHRAM:     origin = 0x0C311190 length = 0x00022210  /* <1MB Multicore shared Memmory */

 #endif

 #ifdef CORE2

     CORE2_L2_SRAM:   origin = 0x12800000 length = 0x00080000   /* 512kB CORE2 L2/SRAM */

     CORE2_L1P_SRAM:  origin = 0x12E00000 length = 0x00008000   /* 32kB CORE2 L1P/SRAM */

     CORE2_L1D_SRAM:  origin = 0x12F00000 length = 0x00008000   /* 32kB CORE2 L1D/SRAM */

     CORE2_DDR3:      origin = 0xa0000000 length = 0x10000000   /* 256MB DDR3 SDRAM for CORE0 */

     CORE2_SHRAM:     origin = 0x0C3333a0 length = 0x00022210  /* <1MB Multicore shared Memmory */

 #endif

 #ifdef CORE3

     CORE3_L2_SRAM:   origin = 0x13800000 length = 0x00080000   /* 512kB CORE3 L2/SRAM */

     CORE3_L1P_SRAM:  origin = 0x13E00000 length = 0x00008000   /* 32kB CORE3 L1P/SRAM */

     CORE3_L1D_SRAM:  origin = 0x13F00000 length = 0x00008000   /* 32kB CORE3 L1D/SRAM */

     CORE3_DDR3:      origin = 0xb0000000 length = 0x10000000   /* 256MB DDR3 SDRAM for CORE0 */

     CORE3_SHRAM:     origin = 0x0C3555b0 length = 0x00022210  /* <1MB Multicore shared Memmory */

 #endif

 #ifdef CORE4

     CORE4_L2_SRAM:   origin = 0x14800000 length = 0x00080000   /* 512kB CORE4 L2/SRAM */

     CORE4_L1P_SRAM:  origin = 0x14E00000 length = 0x00008000   /* 32kB CORE4 L1P/SRAM */

     CORE4_L1D_SRAM:  origin = 0x14F00000 length = 0x00008000   /* 32kB CORE4 L1D/SRAM */

     CORE4_DDR3:      origin = 0xc0000000 length = 0x10000000   /* 256MB DDR3 SDRAM for CORE0 */

     CORE4_SHRAM:     origin = 0x0C3777c0 length = 0x00022210  /* <1MB Multicore shared Memmory */

 #endif

 #ifdef CORE5

     CORE5_L2_SRAM:   origin = 0x15800000 length = 0x00080000   /* 512kB CORE5 L2/SRAM */

     CORE5_L1P_SRAM:  origin = 0x15E00000 length = 0x00008000   /* 32kB CORE5 L1P/SRAM */

     CORE5_L1D_SRAM:  origin = 0x15F00000 length = 0x00008000   /* 32kB CORE5 L1D/SRAM */

     CORE5_DDR3:      origin = 0xd0000000 length = 0x10000000   /* 256MB DDR3 SDRAM for CORE0 */

     CORE5_SHRAM:     origin = 0x0C3999d0 length = 0x00022210  /* <1MB Multicore shared Memmory */

 #endif

 #ifdef CORE6

     CORE6_L2_SRAM:   origin = 0x16800000 length = 0x00080000   /* 512kB CORE6 L2/SRAM */

     CORE6_L1P_SRAM:  origin = 0x16E00000 length = 0x00008000   /* 32kB CORE6 L1P/SRAM */

     CORE6_L1D_SRAM:  origin = 0x16F00000 length = 0x00008000   /* 32kB CORE6 L1D/SRAM */

     CORE6_DDR3:      origin = 0xe0000000 length = 0x10000000   /* 256MB DDR3 SDRAM for CORE0 */

     CORE6_SHRAM:     origin = 0x0C3bbbe0 length = 0x00022210  /* <1MB Multicore shared Memmory */

 #endif

 #ifdef CORE7

     CORE7_L2_SRAM:   origin = 0x17800000 length = 0x00080000   /* 512kB CORE7 L2/SRAM */

     CORE7_L1P_SRAM:  origin = 0x17E00000 length = 0x00008000   /* 32kB CORE7 L1P/SRAM */

     CORE7_L1D_SRAM:  origin = 0x17F00000 length = 0x00008000   /* 32kB CORE7 L1D/SRAM */

     CORE7_DDR3:      origin = 0xf0000000 length = 0x10000000   /* 256MB DDR3 SDRAM for CORE0 */

     CORE7_SHRAM:     origin = 0x0C3dddf0 length = 0x00022210  /* <1MB Multicore shared Memmory */

 #endif

}

SECTIONS

{

#ifdef CORE0

   .twbuf_mem                         >CORE0_DDR3

   .twbuf_ifft_mem                    >CORE0_DDR3

   .brev_mem                        >CORE0_DDR3

   .twbuf_prt_mem                    >CORE0_SHRAM

   .brev_prts_mem                    >CORE0_SHRAM

   .wgn_re_mem                        >CORE0_SHRAM

   .wgn_img_mem                    >CORE0_SHRAM

   .FftTxdLFMWindowed_mem            >CORE0_SHRAM

   .RxdLFM_mem                        >CORE0_DDR3

   .FftRxdLFM_mem                    >CORE0_SHRAM

   .temp_fft_io_mem                >CORE0_SHRAM

   .temp_fft_ii_mem                >CORE0_SHRAM

   .HmmWindowFilterBank_mem        >CORE0_SHRAM

#endif

#ifdef CORE1

   .twbuf_mem                         >CORE1_DDR3

   .twbuf_ifft_mem                    >CORE1_DDR3

   .brev_mem                        >CORE1_DDR3

   .twbuf_prt_mem                    >CORE1_SHRAM

   .brev_prts_mem                    >CORE1_SHRAM

   .wgn_re_mem                        >CORE1_SHRAM

   .wgn_img_mem                    >CORE1_SHRAM

   .FftTxdLFMWindowed_mem            >CORE1_SHRAM

   .RxdLFM_mem                        >CORE1_DDR3

   .FftRxdLFM_mem                    >CORE1_SHRAM

   .temp_fft_io_mem                >CORE1_SHRAM

   .temp_fft_ii_mem                >CORE1_SHRAM

   .HmmWindowFilterBank_mem        >CORE1_SHRAM

#endif

#ifdef CORE2

   .twbuf_mem                         >CORE2_DDR3

   .twbuf_ifft_mem                    >CORE2_DDR3

   .brev_mem                        >CORE2_DDR3

   .twbuf_prt_mem                    >CORE2_SHRAM

   .brev_prts_mem                    >CORE2_SHRAM

   .wgn_re_mem                        >CORE2_SHRAM

   .wgn_img_mem                    >CORE2_SHRAM

   .FftTxdLFMWindowed_mem            >CORE2_SHRAM

   .RxdLFM_mem                        >CORE2_DDR3

   .FftRxdLFM_mem                    >CORE2_SHRAM

   .temp_fft_io_mem                >CORE2_SHRAM

   .temp_fft_ii_mem                >CORE2_SHRAM

   .HmmWindowFilterBank_mem        >CORE2_SHRAM

#endif

#ifdef CORE3

   .twbuf_mem                         >CORE3_DDR3

   .twbuf_ifft_mem                    >CORE3_DDR3

   .brev_mem                        >CORE3_DDR3

   .twbuf_prt_mem                    >CORE3_SHRAM

   .brev_prts_mem                    >CORE3_SHRAM

   .wgn_re_mem                        >CORE3_SHRAM

   .wgn_img_mem                    >CORE3_SHRAM

   .FftTxdLFMWindowed_mem            >CORE3_SHRAM

   .RxdLFM_mem                        >CORE3_DDR3

   .FftRxdLFM_mem                    >CORE3_SHRAM

   .temp_fft_io_mem                >CORE3_SHRAM

   .temp_fft_ii_mem                >CORE3_SHRAM

   .HmmWindowFilterBank_mem        >CORE3_SHRAM

#endif

#ifdef CORE4

   .twbuf_mem                         >CORE4_DDR3

   .twbuf_ifft_mem                    >CORE4_DDR3

   .brev_mem                        >CORE4_DDR3

   .twbuf_prt_mem                    >CORE4_SHRAM

   .brev_prts_mem                    >CORE4_SHRAM

   .wgn_re_mem                        >CORE4_SHRAM

   .wgn_img_mem                    >CORE4_SHRAM

   .FftTxdLFMWindowed_mem            >CORE4_SHRAM

   .RxdLFM_mem                        >CORE4_DDR3

   .FftRxdLFM_mem                    >CORE4_SHRAM

   .temp_fft_io_mem                >CORE4_SHRAM

   .temp_fft_ii_mem                >CORE4_SHRAM

   .HmmWindowFilterBank_mem        >CORE4_SHRAM

#endif

#ifdef CORE5

   .twbuf_mem                         >CORE5_DDR3

   .twbuf_ifft_mem                    >CORE5_DDR3

   .brev_mem                        >CORE5_DDR3

   .twbuf_prt_mem                    >CORE5_SHRAM

   .brev_prts_mem                    >CORE5_SHRAM

   .wgn_re_mem                        >CORE5_SHRAM

   .wgn_img_mem                    >CORE5_SHRAM

   .FftTxdLFMWindowed_mem            >CORE5_SHRAM

   .RxdLFM_mem                        >CORE5_DDR3

   .FftRxdLFM_mem                    >CORE5_SHRAM

   .temp_fft_io_mem                >CORE5_SHRAM

   .temp_fft_ii_mem                >CORE5_SHRAM

   .HmmWindowFilterBank_mem        >CORE5_SHRAM

#endif

#ifdef CORE6

   .twbuf_mem                         >CORE6_DDR3

   .twbuf_ifft_mem                    >CORE6_DDR3

   .brev_mem                        >CORE6_DDR3

   .twbuf_prt_mem                    >CORE6_SHRAM

   .brev_prts_mem                    >CORE6_SHRAM

   .wgn_re_mem                        >CORE6_SHRAM

   .wgn_img_mem                    >CORE6_SHRAM

   .FftTxdLFMWindowed_mem            >CORE6_SHRAM

   .RxdLFM_mem                        >CORE6_DDR3

   .FftRxdLFM_mem                    >CORE6_SHRAM

   .temp_fft_io_mem                >CORE6_SHRAM

   .temp_fft_ii_mem                >CORE6_SHRAM

   .HmmWindowFilterBank_mem        >CORE6_SHRAM

#endif

#ifdef CORE7

   .twbuf_mem                         >CORE7_DDR3

   .twbuf_ifft_mem                    >CORE7_DDR3

   .brev_mem                        >CORE7_DDR3

   .twbuf_prt_mem                    >CORE7_SHRAM

   .brev_prts_mem                    >CORE7_SHRAM

   .wgn_re_mem                        >CORE7_SHRAM

   .wgn_img_mem                    >CORE7_SHRAM

   .FftTxdLFMWindowed_mem            >CORE7_SHRAM

   .RxdLFM_mem                        >CORE7_DDR3

   .FftRxdLFM_mem                    >CORE7_SHRAM

   .temp_fft_io_mem                >CORE7_SHRAM

   .temp_fft_ii_mem                >CORE7_SHRAM

   .HmmWindowFilterBank_mem        >CORE7_SHRAM

#endif

}

3. ca_4c6678_1.cmd ->

MEMORY

{

 #ifdef CORE0

     CORE0_L2_SRAM:   origin = 0x10800000 length = 0x00080000   /* 512kB CORE0 L2/SRAM */

     CORE0_L1P_SRAM:  origin = 0x10E00000 length = 0x00008000   /* 32kB CORE0 L1P/SRAM */

     CORE0_L1D_SRAM:  origin = 0x10F00000 length = 0x00008000   /* 32kB CORE0 L1D/SRAM */

     CORE0_DDR3:      origin = 0x80000000 length = 0x10000000   /* 256MB DDR3 SDRAM for CORE0 */

     CORE0_SHRAM:     origin = 0x0C2eef80 length = 0x00022210  /* <1MB Multicore shared Memmory */

 #endif

 #ifdef CORE1

     CORE1_L2_SRAM:   origin = 0x11800000 length = 0x00080000   /* 512kB CORE1 L2/SRAM */

     CORE1_L1P_SRAM:  origin = 0x11E00000 length = 0x00008000   /* 32kB CORE1 L1P/SRAM */

     CORE1_L1D_SRAM:  origin = 0x11F00000 length = 0x00008000   /* 32kB CORE1 L1D/SRAM */

     CORE1_DDR3:      origin = 0x90000000 length = 0x10000000   /* 256MB DDR3 SDRAM for CORE0 */

     CORE1_SHRAM:     origin = 0x0C311190 length = 0x00022210  /* <1MB Multicore shared Memmory */

 #endif

 #ifdef CORE2

     CORE2_L2_SRAM:   origin = 0x12800000 length = 0x00080000   /* 512kB CORE2 L2/SRAM */

     CORE2_L1P_SRAM:  origin = 0x12E00000 length = 0x00008000   /* 32kB CORE2 L1P/SRAM */

     CORE2_L1D_SRAM:  origin = 0x12F00000 length = 0x00008000   /* 32kB CORE2 L1D/SRAM */

     CORE2_DDR3:      origin = 0xa0000000 length = 0x10000000   /* 256MB DDR3 SDRAM for CORE0 */

     CORE2_SHRAM:     origin = 0x0C3333a0 length = 0x00022210  /* <1MB Multicore shared Memmory */

 #endif

 #ifdef CORE3

     CORE3_L2_SRAM:   origin = 0x13800000 length = 0x00080000   /* 512kB CORE3 L2/SRAM */

     CORE3_L1P_SRAM:  origin = 0x13E00000 length = 0x00008000   /* 32kB CORE3 L1P/SRAM */

     CORE3_L1D_SRAM:  origin = 0x13F00000 length = 0x00008000   /* 32kB CORE3 L1D/SRAM */

     CORE3_DDR3:      origin = 0xb0000000 length = 0x10000000   /* 256MB DDR3 SDRAM for CORE0 */

     CORE3_SHRAM:     origin = 0x0C3555b0 length = 0x00022210  /* <1MB Multicore shared Memmory */

 #endif

 #ifdef CORE4

     CORE4_L2_SRAM:   origin = 0x14800000 length = 0x00080000   /* 512kB CORE4 L2/SRAM */

     CORE4_L1P_SRAM:  origin = 0x14E00000 length = 0x00008000   /* 32kB CORE4 L1P/SRAM */

     CORE4_L1D_SRAM:  origin = 0x14F00000 length = 0x00008000   /* 32kB CORE4 L1D/SRAM */

     CORE4_DDR3:      origin = 0xc0000000 length = 0x10000000   /* 256MB DDR3 SDRAM for CORE0 */

     CORE4_SHRAM:     origin = 0x0C3777c0 length = 0x00022210  /* <1MB Multicore shared Memmory */

 #endif

 #ifdef CORE5

     CORE5_L2_SRAM:   origin = 0x15800000 length = 0x00080000   /* 512kB CORE5 L2/SRAM */

     CORE5_L1P_SRAM:  origin = 0x15E00000 length = 0x00008000   /* 32kB CORE5 L1P/SRAM */

     CORE5_L1D_SRAM:  origin = 0x15F00000 length = 0x00008000   /* 32kB CORE5 L1D/SRAM */

     CORE5_DDR3:      origin = 0xd0000000 length = 0x10000000   /* 256MB DDR3 SDRAM for CORE0 */

     CORE5_SHRAM:     origin = 0x0C3999d0 length = 0x00022210  /* <1MB Multicore shared Memmory */

 #endif

 #ifdef CORE6

     CORE6_L2_SRAM:   origin = 0x16800000 length = 0x00080000   /* 512kB CORE6 L2/SRAM */

     CORE6_L1P_SRAM:  origin = 0x16E00000 length = 0x00008000   /* 32kB CORE6 L1P/SRAM */

     CORE6_L1D_SRAM:  origin = 0x16F00000 length = 0x00008000   /* 32kB CORE6 L1D/SRAM */

     CORE6_DDR3:      origin = 0xe0000000 length = 0x10000000   /* 256MB DDR3 SDRAM for CORE0 */

     CORE6_SHRAM:     origin = 0x0C3bbbe0 length = 0x00022210  /* <1MB Multicore shared Memmory */

 #endif

 #ifdef CORE7

     CORE7_L2_SRAM:   origin = 0x17800000 length = 0x00080000   /* 512kB CORE7 L2/SRAM */

     CORE7_L1P_SRAM:  origin = 0x17E00000 length = 0x00008000   /* 32kB CORE7 L1P/SRAM */

     CORE7_L1D_SRAM:  origin = 0x17F00000 length = 0x00008000   /* 32kB CORE7 L1D/SRAM */

     CORE7_DDR3:      origin = 0xf0000000 length = 0x10000000   /* 256MB DDR3 SDRAM for CORE0 */

     CORE7_SHRAM:     origin = 0x0C3dddf0 length = 0x00022210  /* <1MB Multicore shared Memmory */

 #endif

}

SECTIONS

{

#ifdef CORE0

   .twbuf_mem                         >CORE0_DDR3

   .twbuf_ifft_mem                    >CORE0_DDR3

   .brev_mem                        >CORE0_DDR3

   .twbuf_prt_mem                    >CORE0_DDR3

   .brev_prts_mem                    >CORE0_DDR3

   .wgn_re_mem                        >CORE0_DDR3

   .wgn_img_mem                    >CORE0_DDR3

   .FftTxdLFMWindowed_mem            >CORE0_DDR3

   .RxdLFM_mem                        >CORE0_DDR3

   .FftRxdLFM_mem                    >CORE0_DDR3

   .temp_fft_io_mem                >CORE0_DDR3

   .temp_fft_ii_mem                >CORE0_DDR3

   .HmmWindowFilterBank_mem        >CORE0_DDR3

#endif

#ifdef CORE1

   .twbuf_mem                         >CORE1_DDR3

   .twbuf_ifft_mem                    >CORE1_DDR3

   .brev_mem                        >CORE1_DDR3

   .twbuf_prt_mem                    >CORE1_DDR3

   .brev_prts_mem                    >CORE1_DDR3

   .wgn_re_mem                        >CORE1_DDR3

   .wgn_img_mem                    >CORE1_DDR3

   .FftTxdLFMWindowed_mem            >CORE1_DDR3

   .RxdLFM_mem                        >CORE1_DDR3

   .FftRxdLFM_mem                    >CORE1_DDR3

   .temp_fft_io_mem                >CORE1_DDR3

   .temp_fft_ii_mem                >CORE1_DDR3

   .HmmWindowFilterBank_mem        >CORE1_DDR3

#endif

#ifdef CORE2

   .twbuf_mem                         >CORE2_DDR3

   .twbuf_ifft_mem                    >CORE2_DDR3

   .brev_mem                        >CORE2_DDR3

   .twbuf_prt_mem                    >CORE2_DDR3

   .brev_prts_mem                    >CORE2_DDR3

   .wgn_re_mem                        >CORE2_DDR3

   .wgn_img_mem                    >CORE2_DDR3

   .FftTxdLFMWindowed_mem            >CORE2_DDR3

   .RxdLFM_mem                        >CORE2_DDR3

   .FftRxdLFM_mem                    >CORE2_DDR3

   .temp_fft_io_mem                >CORE2_DDR3

   .temp_fft_ii_mem                >CORE2_DDR3

   .HmmWindowFilterBank_mem        >CORE2_DDR3

#endif

#ifdef CORE3

   .twbuf_mem                         >CORE3_DDR3

   .twbuf_ifft_mem                    >CORE3_DDR3

   .brev_mem                        >CORE3_DDR3

   .twbuf_prt_mem                    >CORE3_DDR3

   .brev_prts_mem                    >CORE3_DDR3

   .wgn_re_mem                        >CORE3_DDR3

   .wgn_img_mem                    >CORE3_DDR3

   .FftTxdLFMWindowed_mem            >CORE3_DDR3

   .RxdLFM_mem                        >CORE3_DDR3

   .FftRxdLFM_mem                    >CORE3_DDR3

   .temp_fft_io_mem                >CORE3_DDR3

   .temp_fft_ii_mem                >CORE3_DDR3

   .HmmWindowFilterBank_mem        >CORE3_DDR3

#endif

#ifdef CORE4

   .twbuf_mem                         >CORE4_DDR3

   .twbuf_ifft_mem                    >CORE4_DDR3

   .brev_mem                        >CORE4_DDR3

   .twbuf_prt_mem                    >CORE4_DDR3

   .brev_prts_mem                    >CORE4_DDR3

   .wgn_re_mem                        >CORE4_DDR3

   .wgn_img_mem                    >CORE4_DDR3

   .FftTxdLFMWindowed_mem            >CORE4_DDR3

   .RxdLFM_mem                        >CORE4_DDR3

   .FftRxdLFM_mem                    >CORE4_DDR3

   .temp_fft_io_mem                >CORE4_DDR3

   .temp_fft_ii_mem                >CORE4_DDR3

   .HmmWindowFilterBank_mem        >CORE4_DDR3

#endif

#ifdef CORE5

   .twbuf_mem                         >CORE5_DDR3

   .twbuf_ifft_mem                    >CORE5_DDR3

   .brev_mem                        >CORE5_DDR3

   .twbuf_prt_mem                    >CORE5_DDR3

   .brev_prts_mem                    >CORE5_DDR3

   .wgn_re_mem                        >CORE5_DDR3

   .wgn_img_mem                    >CORE5_DDR3

   .FftTxdLFMWindowed_mem            >CORE5_DDR3

   .RxdLFM_mem                        >CORE5_DDR3

   .FftRxdLFM_mem                    >CORE5_DDR3

   .temp_fft_io_mem                >CORE5_DDR3

   .temp_fft_ii_mem                >CORE5_DDR3

   .HmmWindowFilterBank_mem        >CORE5_DDR3

#endif

#ifdef CORE6

   .twbuf_mem                         >CORE6_DDR3

   .twbuf_ifft_mem                    >CORE6_DDR3

   .brev_mem                        >CORE6_DDR3

   .twbuf_prt_mem                    >CORE6_DDR3

   .brev_prts_mem                    >CORE6_DDR3

   .wgn_re_mem                        >CORE6_DDR3

   .wgn_img_mem                    >CORE6_DDR3

   .FftTxdLFMWindowed_mem            >CORE6_DDR3

   .RxdLFM_mem                        >CORE6_DDR3

   .FftRxdLFM_mem                    >CORE6_DDR3

   .temp_fft_io_mem                >CORE6_DDR3

   .temp_fft_ii_mem                >CORE6_DDR3

   .HmmWindowFilterBank_mem        >CORE6_DDR3

#endif

#ifdef CORE7

   .twbuf_mem                         >CORE7_DDR3

   .twbuf_ifft_mem                    >CORE7_DDR3

   .brev_mem                        >CORE7_DDR3

   .twbuf_prt_mem                    >CORE7_DDR3

   .brev_prts_mem                    >CORE7_DDR3

   .wgn_re_mem                        >CORE7_DDR3

   .wgn_img_mem                    >CORE7_DDR3

   .FftTxdLFMWindowed_mem            >CORE7_DDR3

   .RxdLFM_mem                        >CORE7_DDR3

   .FftRxdLFM_mem                    >CORE7_DDR3

   .temp_fft_io_mem                >CORE7_DDR3

   .temp_fft_ii_mem                >CORE7_DDR3

   .HmmWindowFilterBank_mem        >CORE7_DDR3

#endif

}

4. linker file.JPG

0 Raja over 10 years ago in reply to Umesha M Y

TI__Guru* 81335 points

Hi Umesha,

I have reviewed above attached files. Are you running this on EVM or custom board? The EVM has 512MB of DDR whereas you have specified the 256MB/core on the linker command file.

Also, I recommend you to use the aligned address regions for COREx_SHRAM.

Thank you.

0 Umesha M Y over 10 years ago in reply to Raja

Prodigy 60 points

Hi Raja sir,

I have been using both EVM and Commagility's 4C6678 board for my project work.
I change the DDR3 memory's address accordingly w.r.t the board.
The above linker command file is corresponds to 4C6678 where in the board has got totally of 8GB DDR3. So that is the reason I have specified 256MB/core.

sir in my source code I use aligned address regions for COREx_SHRAM as well as for DDR3.

0 Raja over 10 years ago in reply to Umesha M Y

TI__Guru* 81335 points

Hi Umesha,
Please try to resolve the issue in EVM then you can try it on the other custom board.

0 Umesha M Y over 10 years ago in reply to Raja

Prodigy 60 points

Raja Sir,

Same problem exists in both the boards.

Ok let me work on EVM only.. Can you pls through some lights that why I have been getting this problem?

anything i am missing configuring the memory?

Processors

Processors forum

Results getting corrupted on my multicore project