Unable to load U-boot for AM3351 processor

I'll also add that in the CCS console window I see the following error message details,

CortxA8: Trouble Writing Memory Block at 0x80800000 on Page 0 of Length 0x7ff0: (Error -1065 @ 0x3D5A) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.407.3)
CortxA8: File Loader: Verification failed: Target failed to write 0x80800000
CortxA8: GEL: File: /home/clightcap/ti-processor-sdk-linux-am335x-evm-03.00.00.04/board-support/u-boot-2016.05+gitAUTOINC+b4e185a8c3-gb4e185a8c3/u-boot: Load failed.

Best regards,
Chris

Chris Lightcap said:

As I'm using a custom AM3351 board, I needed to modify the DDR memory configuration and pinmux settings to be compatible with my board.

The address 0x80800000 at which the "Trouble Writing Memory Block" occurs is in DDR memory.

I suspect that either:

- The SPL code hasn't configured the DDR memory correctly to allow the U-boot file to be loaded into DDR memory.

- There is a fault with the DDR memory on the custom AM3351 board.

Suggest that after running the SPL code which configures the DDR memory, then pause the processor and attempt to use the CCS memory browser to see if you can read / write the DDR memory starting at 0x80000000 successfully.

Hi Chester,

Thank you for the suggestion. I double checked my DDR reading/writing and there was in fact a problem with my DDR configuration. I've since corrected the problem and am able to pause the program and read/write to the 0x80000000 address. I'm also now able to load the program u-boot once the SPL code has completed, however, when I try to run the program, it simply hangs. After re-loading the SPL program and then u-boot, I step through the code one line at a time and see that it hangs after only a few steps, and there is no output to the console.

Could this still be a problem with my DDR memory configuration?

There are two strange things that are happening with my execution. First, it only successfully runs the SPL code the second time after resetting. The program consistently hangs the first time I run it. Second, after completing the SPL code and pausing the program, the Sitara processor will consistently reset itself after perhaps 10 - 15 seconds. Is there some kind of watchdog enabled that may be interfering with my SPL and u-boot execution?

Here's the UART0 output from my SPL code. Thank you again for your support!

Best regards,

Chris

U-Boot SPL 2016.05-00230-g120a8a3-dirty (Oct 18 2016 - 14:47:01) 

musb-hdrc:ConfigData=0xde (UTMI-8, dyn FIFOs, HB-ISO Rx, HB-ISO Tx, SoftConn)
musb-hdrc: MHDRC RTL version 2.0
musb-hdrc: setup fifo_mode 4
musb-hdrc: 28/31 max ep, 16384/16384 memory
musb-hdrc: hw_ep 0shared, max 64
musb-hdrc: hw_ep 1tx, max 512
musb-hdrc: hw_ep 1rx, max 512
musb-hdrc: hw_ep 2tx, max 512
musb-hdrc: hw_ep 2rx, max 512
musb-hdrc: hw_ep 3tx, max 512
musb-hdrc: hw_ep 3rx, max 512
musb-hdrc: hw_ep 4tx, max 512
musb-hdrc: hw_ep 4rx, max 512
musb-hdrc: hw_ep 5tx, max 512
musb-hdrc: hw_ep 5rx, max 512
musb-hdrc: hw_ep 6tx, max 512
musb-hdrc: hw_ep 6rx, max 512
musb-hdrc: hw_ep 7tx, max 512
musb-hdrc: hw_ep 7rx, max 512
musb-hdrc: hw_ep 8tx, max 512
musb-hdrc: hw_ep 8rx, max 512
musb-hdrc: hw_ep 9tx, max 512
musb-hdrc: hw_ep 9rx, max 512
musb-hdrc: hw_ep 10tx, max 256
musb-hdrc: hw_ep 10rx, max 64
musb-hdrc: hw_ep 11tx, max 256
musb-hdrc: hw_ep 11rx, max 64
musb-hdrc: hw_ep 12tx, max 256
musb-hdrc: hw_ep 12rx, max 64
musb-hdrc: hw_ep 13shared, max 4096
musb-hdrc: hw_ep 14shared, max 1024
musb-hdrc: hw_ep 15shared, max 1024
USB Peripheral mode controller at 47401000 using PIO, IRQ 0
musb-hdrc:ConfigData=0xde (UTMI-8, dyn FIFOs, HB-ISO Rx, HB-ISO Tx, SoftConn)
musb-hdrc: MHDRC RTL version 2.0
musb-hdrc: setup fifo_mode 4
musb-hdrc: 28/31 max ep, 16384/16384 memory
musb-hdrc: hw_ep 0shared, max 64
musb-hdrc: hw_ep 1tx, max 512
musb-hdrc: hw_ep 1rx, max 512
musb-hdrc: hw_ep 2tx, max 512
musb-hdrc: hw_ep 2rx, max 512
musb-hdrc: hw_ep 3tx, max 512
musb-hdrc: hw_ep 3rx, max 512
musb-hdrc: hw_ep 4tx, max 512
musb-hdrc: hw_ep 4rx, max 512
musb-hdrc: hw_ep 5tx, max 512
musb-hdrc: hw_ep 5rx, max 512
musb-hdrc: hw_ep 6tx, max 512
musb-hdrc: hw_ep 6rx, max 512
musb-hdrc: hw_ep 7tx, max 512
musb-hdrc: hw_ep 7rx, max 512
musb-hdrc: hw_ep 8tx, max 512
musb-hdrc: hw_ep 8rx, max 512
musb-hdrc: hw_ep 9tx, max 512
musb-hdrc: hw_ep 9rx, max 512
musb-hdrc: hw_ep 10tx, max 256
musb-hdrc: hw_ep 10rx, max 64
musb-hdrc: hw_ep 11tx, max 256
musb-hdrc: hw_ep 11rx, max 64
musb-hdrc: hw_ep 12tx, max 256
musb-hdrc: hw_ep 12rx, max 64
musb-hdrc: hw_ep 13shared, max 4096
musb-hdrc: hw_ep 14shared, max 1024
musb-hdrc: hw_ep 15shared, max 1024
USB Host mode controller at 47401800 using PIO, IRQ 0
Timed out in wait_for_event: status=0000
Check if pads/pull-ups of bus 0 are properly configured
Timed out in wait_for_event: status=0000
Check if pads/pull-ups of bus 0 are properly configured
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

Moving to appropriate forum.

Hi Jace,

Thanks for your quick reply. To which forum are you moving this post? Please send me a link when you get a chance.

Thanks,
Chris

Hello,

One other comment about the code hanging every other time I reset the board. It fails and hangs at the very beginning of the SPL code, at the instructions _prefetch_abort and _data_abort in those cases.

Best regards,
Chris

54 b reset
__start(), _start():
402f0400: EA000016 b reset
55 ldr pc, _undefined_instruction
402f0404: E59FF014 ldr pc, [pc, #0x14]
56 ldr pc, _software_interrupt
402f0408: E59FF014 ldr pc, [pc, #0x14]
57 ldr pc, _prefetch_abort
402f040c: E59FF014 ldr pc, [pc, #0x14]
58 ldr pc, _data_abort
402f0410: E59FF014 ldr pc, [pc, #0x14]

Chris,

This post is already moved and links changed automatically. I moved the post to the Sitara (AM3351) forum for it was showing up in the MSP (MCU) forum.

Hi Chester,

That was absolutely the problem! As you suggested, it was resetting the HW watchdog and THUMB mode upon reset and I wasn't adjusting these before loading the u-boot program.

I've corrected the HW watchdog problem by disabling this feature in the ti_am335x_common.h file

// #define CONFIG_HW_WATCHDOG

I'm now able to load the u-boot program, but when running the code, there is no output to my UART console, and it terminates at the bootstage_error function, with id BOOTSTAGE_ID_NEED_RESET. 

static inline ulong bootstage_error(enum bootstage_id id)

{
show_boot_progress(-id);
return 0;
}

hang():

808406d4: 4804 ldr r0, [pc, #0x10]
23 {
808406d6: B508 push {r3, lr}
26 puts("### ERROR ### Please RESET the board ###\n");
808406d8: F7D2FF92 bl #0x80813600
357 show_boot_progress(-id);
bootstage_error():
808406dc: F06F001D mvn r0, #0x1d
808406e0: F7CCF8C5 bl #0x8080c86e
808406e4: E7FE b #0x808406e4

Any suggestions as to why I'm not seeing the U-Boot# console output?

Best regards,

Chris

 

Hi Chester,

I stepped through the u-boot code (after loading and running SPL code), and found that it hangs in the board_init_f() function when calling initcall_run_list(). It seems to be failing at the initcall sequence. Any suggestions as to why it would be failing here?

Also, I'm not seeing any of the printf statements in my UART console. Why are they not displayed and how can I enable them for debugging? Note I've already set the #define DEBUG macro in the am335x_evm.h header.

Thank you again for your support!

Best regards,

Chris

if (initcall_run_list(init_sequence_f))

hang();

int initcall_run_list(const init_fnc_t init_sequence[])
{
const init_fnc_t *init_fnc_ptr;

for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
unsigned long reloc_ofs = 0;
int ret;

if (gd->flags & GD_FLG_RELOC)
reloc_ofs = gd->reloc_off;
#ifdef CONFIG_EFI_APP
reloc_ofs = (unsigned long)image_base;
#endif
debug("initcall: %p", (char *)*init_fnc_ptr - reloc_ofs);
if (gd->flags & GD_FLG_RELOC)
debug(" (relocated to %p)\n", (char *)*init_fnc_ptr);
else
debug("\n");
ret = (*init_fnc_ptr)();
if (ret) {
printf("initcall sequence %p failed at call %p (err=%d)\n",
init_sequence,
(char *)*init_fnc_ptr - reloc_ofs, ret);
return -1;
}
}
return 0;
}

Chris Lightcap said:

It seems to be failing at the initcall sequence.

Is it is one particular init_fnc_ptr in the list of init_sequence initialization function pointers which cause the fault, and if so what is the function?

To be honest I haven't debugged U-boot startup before, but will try that on an AM335x board.

Are you using the U-boot which comes with the processor-sdk-03.00.00.04?

Hi Chester,

I stepped through the function pointers and found that u-boot is failing inside

int fdtdec_setup(void) -> fdtdec_prepare_fdt() -> fdt_check_header(const void *fdt)

int fdt_check_header(const void *fdt) {

  if (fdt_magic(fdt) == FDT_MAGIC) {
    /* Complete tree */
    if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION)
      return -FDT_ERR_BADVERSION;
    if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION)
      return -FDT_ERR_BADVERSION;
  } else if (fdt_magic(fdt) == FDT_SW_MAGIC) {
    /* Unfinished sequential-write blob */
    if (fdt_size_dt_struct(fdt) == 0)
        return -FDT_ERR_BADSTATE;
  } else {
    return -FDT_ERR_BADMAGIC; // <-- RETURNING HERE
  }

  return 0;

}

int fdtdec_prepare_fdt(void) {

  if (!gd->fdt_blob || ((uintptr_t)gd->fdt_blob & 3) ||
  fdt_check_header(gd->fdt_blob)) {
  ...

    puts("No valid device tree binary found - please append one to U-Boot binary, use u-boot-dtb.bin or define CONFIG_OF_EMBED. For sandbox, use -d <file.dtb>\n");

    if (gd->fdt_blob) {
      printf("fdt_blob=%p\n", gd->fdt_blob);
      print_buffer((ulong)gd->fdt_blob, gd->fdt_blob, 4, 32, 0);
    }
    return -1;
  }
  return 0;
}

U-boot  appears to be searching for a device tree binary. I've been following the instructions for debugging u-boot found here

http://processors.wiki.ti.com/index.php/Sitara_Linux_Training:_uboot_linux_debug_with_ccsv5

and there is no mention of using a device tree binary at this stage of debugging. Is this because I'm using a custom board without any specific header in EEPROM? Where can I find more information about appending a .dtb file to a u-boot binary?

Please help me enable the printf and puts functions to display to my console. I would have found this problem much faster if I could see the console output. How can I enable logging to my UART0 console earlier in the u-boot program? I'm able to see the output from SPL so I know that my UART is configured properly.

Thank you again for your support.

Best regards,

Chris

Hi Chester,

Thanks for your help so far, I'm going to spin up another thread question regarding the FDT errors as I'm now able to load u-boot, which was the original thread question. If you have any suggestions, please respond to my new thread.

https://e2e.ti.com/support/arm/sitara_arm/f/791/t/550011

Thanks,

Chris