Hi Champs,
We have an am335x customer that is having issues with enabling full ZQ calibration for DDR3 memory. More particullary, they need the Read-Write Leveling to fix all data skew issue that they might be having. They are doing tuning for their DDR3 memory [ 2 GBit, 16MX16X8 1066 Mhz]and are looking at the initialization of the SOC memory controller registers. They thought that they were setting ZQ= 1 , Register= C8h [ value= 5007 4BE4] for calibration Correctly, but the registers are not setting the Read-Write Leveling Ramp control register for any read-write leveling[ reg D8h]. They need this bit to be set to do the Read _write leveling for ZQ.
Can you please tell us what recommended memory controller register value for D8h [ in a fast memory usage here] values for this register for the following bits;
Bit 0-7= XX
Bit 15-8= XX
23-16=XX
30-24=XX
bit 31 =1 to enable leveling.
The reason they need this setup is because they are having memory failures during temperature testing, and the vendor told them to make sure to enable ZQ calibration protocol. The customer thought that they did this, but while watching the registers in real-time they saw that we were not using full DDR3 ZQ calibration protocol. They are seeing that register D8h is 0, but should bet set to 1 to enable this. Can you please tell us how to correctly enable DDR3 ZQ calibration.
Thanks,
Kelvin
