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Original question:

TMS320C6713B: Code execution from flash directly

RTOS/TMS320C6713B: DSP/BIOS problem accessing CE0 Memory Space

kowalski
Expert 1285 points

Part Number: TMS320C6713B

Tool/software: TI-RTOS

Hi,

I have a project (without BIOS) for C6713 processor. I am trying to port code written for C6713 DSP processor from baremetal to DSP/BIOS v5.31.2 based. I have few ICs (CAN controller etc.) mapped on  CE0 space of c6713. When i configure them using the old code (without bios) it works fine but when i try to initialize these from main while BIOS configuraiton files included to the project, the CE0 space doesn't seems to be configuring external devices on CE0. Following is rough code:

int main () {

   //initialize CE0 space for asynchronous memory access

  initCE0();

 

//BIOS_start(); ---> to be called by the kernel.

}

I am totally confused what's the connection b/w BIOS kernel and CE0 EMIF space. Do i have to do some memory configurations in the .tcf config file for CE0??

I compared register setting for both code for CE0 of EMIF. both are same.

Impatiently waiting for your kind response.

Kind Regards,

  • 0
    TI__Guru*** 125430 points
    In general I wouldn't expect BIOS to touch the EMIF at all. A couple things come to mind:

    1. Compare the EMIF registers in your working scenario vs the non-working scenario. Are they configured the same? (Look at the registers, not the code.)

    2. The BIOS configuration allows MAR bits to be specified. If those bits are set, that will make the memory cacheable. This could be causing the updates to this memory space to be stuck in cache. If you have peripherals sitting in this space, they should be non-cacheable. You can check the status of these MAR bits using CCS. They are memory mapped registers. Please check the following locations:

    * MAR0: 0x01848200
    * MAR1: 0x01848204
    * MAR2: 0x01848208
    * MAR3: 0x0184820C

    Those 4 registers cover the complete CE0 space. All 4 should be 0 in order to keep the space non-cacheable.
  • 0 in reply to Brad Griffis
    Expert 1285 points
    Wonderful Sir. Disabling Cache setting in DSP/BIOS resolved the issue. As you mentioned the CE0 was cacheable.

    Many thanks sir.
  • 0 in reply to kowalski
    TI__Guru*** 125430 points
    I'm glad to hear that fixed things. The examples were likely created with the 6713 DSK in mind, which has SDRAM on CE0. It was appropriate in that case to mark the memory as cacheable, though for your hardware it's not right. I'm glad it was an easy solution.
  • 0 in reply to Brad Griffis
    Expert 1285 points
    Thanks once again. where can I find explanation/bits settings of your mentioned registers?

    * MAR0: 0x01848200
    * MAR1: 0x01848204
    * MAR2: 0x01848208
    * MAR3: 0x0184820C

    The datasheet doesn't have bit fields explanation for these registers.
  • 0 in reply to kowalski
    TI__Guru*** 125430 points

    Please see the following:

    TMS320C621x/C671x DSP Two-Level Internal Memory Reference Guide
    http://www.ti.com/lit/spru609
    Chapter 6.12 L2 Memory Attribute Registers