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AM5728: TLV320AIC304 MCLK, WCLK and BCLK have no clock signal

Part Number: AM5728
Other Parts Discussed in Thread: BEAGLEBOARD-X15, TLV320AIC3104

I have a AM5728 custom board.

I use ti-processor-sdk-linux-am57xx-evm-06.03.00.106-Linux-x86-Install.bin

I use am57xx-beagle-x15-common.dtsi

This is the audio configuration on the device tree

....................................................................................

sound0: sound0 {
compatible = "simple-audio-card";
simple-audio-card,name = "BeagleBoard-X15";
simple-audio-card,widgets =
"Line", "Line Out",
"Line", "Line In";
simple-audio-card,routing =
"Line Out", "LLOUT",
"Line Out", "RLOUT",
"MIC2L", "Line In",
"MIC2R", "Line In";
simple-audio-card,format = "dsp_b";
simple-audio-card,bitclock-master = <&sound0_master>;
simple-audio-card,frame-master = <&sound0_master>;
simple-audio-card,bitclock-inversion;

simple-audio-card,cpu {
sound-dai = <&mcasp3>;
};

sound0_master: simple-audio-card,codec {
sound-dai = <&tlv320aic3104>;
clocks = <&clkout2_clk>;
};
};

tlv320aic3104: tlv320aic3104@18 {
#sound-dai-cells = <0>;
compatible = "ti,tlv320aic3104";
reg = <0x18>;
assigned-clocks = <&clkoutmux2_clk_mux>;
assigned-clock-parents = <&sys_clk2_dclk_div>;

status = "okay";
adc-settle-ms = <40>;

AVDD-supply = <&vdd_3v3>;
IOVDD-supply = <&vdd_3v3>;
DRVDD-supply = <&vdd_3v3>;
DVDD-supply = <&aic_dvdd>;
};

&mcasp3 {
#sound-dai-cells = <0>;
assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 22>;
assigned-clock-parents = <&sys_clkin2>;
status = "okay";

op-mode = <0>; /* MCASP_IIS_MODE */
tdm-slots = <2>;
/* 4 serializers */
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
1 2 0 0
>;
tx-num-evt = <32>;
rx-num-evt = <32>;
};

.........................................................................................................

This is my schematic

7674.DJ-AM57X-Audio (3).pdf

root@am57xx-evm:~# dmesg |grep mcasp
[ 3.786416] asoc-simple-card sound0: tlv320aic3x-hifi <-> 48468000.mcasp mapping ok
root@am57xx-evm:~#

My question is how to configure the clocks of MCLK?  WCLK and BCLK, why I measure MCLK, WCLK and BCLK without clock signals?