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AM3358: Board power-up sequence design to avoid AM3358 latch-up

Di Jiao
Intellectual 815 points

Part Number: AM3358
Other Parts Discussed in Thread: MAX232, TL5209, MAX3232

Hi,

  I want to take some power-up sequence design to avoid AM3358 latch-up problems as below:

  1. Use TPS65217C to power the AM3358;

  2. Use the TPS65217C PGOOD pin to enable other board peripherals power IC.

  Is that enough?

  Best regards,

  Di

  • 0
    TI__Guru 64995 points

    Your question does not provide enough details of planned power sequence for each power rail, so not able to provide a specific answer.

    You should make sure each AM335x power rail follows the recommended power sequencing defined in the datasheet. You also need to make sure IOs of all attached devices are powered from the same power source that sources the respective AM335x IOs so they ramp up/down together preventing non-fail-safe conditions. You should not have a latch-up condition as long as your system is designed such that it never sources an IO with a voltage potential outside the Recommended Operating Conditions and Absolute Maximum Ratings tables.

    Regards,
    Paul

  • 0 in reply to peaves
    Intellectual 815 points

    Hi Paul,

      Thanks for your reply.

      Here are some details about my design.

      1. The TPS65217x is a single-chip power management IC (PMIC) specifically designed to power the AM335x ARM® Cortex® -A8 processor.

      2. My main concern is that to make sure the other board peripherals related to AM3358 is powered when AM3358 is ready. 

      The PGOOD pin on TPS65217x is set high when the PMIC power-up sequence is complete. 

      

      Best regards,

      Di

  • 0 in reply to Di Jiao
    TI__Guru 64995 points

    When you say, other board peripherals, does that mean devices that have their IOs connected to the AM3358 IOs?

    If so, the IOs of these devices need to be sourced from the same supply as the AM3358 IOs connected to devices in question. For example, if you have an Ethernet PHY connected to AM3358 the IOs of the Ethernet PHY should be powered from the same source as the AM3358 IOs which are connected to the Ethernet PHY. In this case, you should not supply the Ethernet PHY from a different supply that only begins to ramp after the power good from the AM3358 IO supply enables the Ethernet PHY IO supply since there would be a delay between IOs connected to the same signal. This would power the AM3358 IOs before the Ethernet PHY which may allow the AM3358 IOs to source a potential to the unpowered Ethernet PHY which is very unlikely to have fail-safe IOs.

    The AM3358 IOs are banked such that groups of IOs are powered from different IO power rails. You can find this association in the Datasheet Pin Attributes table.

    You need to assign power supplies to these banks of power rails such that AM3358 IOs and associated peripheral devices are powered from the same power supplies. This allows them to ramp up/down together. If more than one supply is required the AM335x IOs may need to be partitioned across multiple power supplies, while keeping the association of AM3358 IOs and attached peripheral devices.

    The system designer must develop a power solution that meets the sequence requirements specific to their product design. Each device in the system needs to be evaluated for sequencing requirements and current consumption before designing a power solution. Only the systems designer has enough detailed knowledge of their system and potential trade-offs which may need to be considered when performing this task.

    Regards,
    Paul

  • 0 in reply to peaves
    Intellectual 815 points

    Hi Paul,

       Thanks for your patience.

      1. The other board peripherals mean devices that have their IOs connected to the AM3358 IOs, such as RS232/485 and CAN;

      2. In my early design, I used the same 5V to power the TPS65217C for AM3358 and MAX232 and the AM3358 failed to boot. And the AM3358 can boot normally if I remove the MAX232. So I think the problem is that the MAX232 is powered before the AM3358 and the ROUT pin from the MAX232 to AM3358 causes the latch-up in AM3358.

      3. The IOs of these devices need to be sourced from the same supply as the AM3358 IOs connected to devices. I agree with what you said but there are some difficulties in practice. The devices connected to AM3358 may need different power such as MAX232(5V powered). What's more, I use AM3358 GPMC port to communicate with a FPGA and TPS65271C can NOT provide the total power so the FPGA should be powered with a different 3.3V source.

       4. Like what you mentioned, I may face the other board peripherals latch-up problems if I power these peripherals after the AM3358 powered.

      So what should I do?

    Best regards,

    Di  

  • 0 in reply to peaves
    Intellectual 815 points

    In beaglebone-black board, the AM335x is powered by TPS65217C and the PHY is powered by TL5209.

    The TL5209 EN pin is connected to TPS65217C LDO4. LDO4 is the last one in TPS65217C power-up sequences.

  • 0 in reply to Di Jiao
    TI__Guru 64995 points

    As mentioned before you are the system designer and the best person to understand issues like the MAX232 being powered from a 5V rail.

    TI makes a MAX3232 which can be powered from a 3.3V supply. Maybe this would be an option for the example you mentioned.

    Another option may be to insert bus FET switches in the signal paths that get powered before the IO supply of either device with the bus FET switch being disabled by default. Once all supplies are valid, you can turn on the switches. I mention bus FET switches because they do not insert any significant propagation delay in the path. Note: If you use bus FET switches, make sure you select ones that drive rail-to-rail.

    If the interface has enough margin, you may be able to insert active level-shifters where each side is powered from its respective IO power rail, but you must select level-shifts that disable their outputs until both supplies are valid.

    I suspect there are many other options, but not sure which works best for your product. 

    This design challenge is a common problem for any complex system that requires multiple power rails. Your issue is not unique to AM335x. I suspect the FPGA and many other components being used in your design have similar requirements.

    Regards,
    Paul

  • 0 in reply to Di Jiao
    TI__Guru 64995 points

    I'm not familiar with details of BBB design. I can't say for sure, but maybe the BBB designer didn't understand the risk. It is also possible they understood the risk, but decided the risk wasn't worth the additional cost of eliminating it.

    Regards,
    Paul