j721e RTOS EDP

Hi jie Xu,

In PDK, can you set the flag DISP_APP_TEST_EDP to 1 in dss_display_test.h header file? This will enable eDP output in the DSS example and then you should see some output on display.

Regards,

Brijesh

Hi  Brijesh Jadav，

Thanks for your replay ， i have tried to set  

Hi jie xu,

Do you rebuild the dss example? Can you please put some debug statements to make sure it is outputting on eDP? 

I had tested it earlier, it was working fine. 

Regards,

Brijesh

Hi  Brijesh Jadav，

Thank you for your prompt reply。

I used the dss_display_test and I rebuild it , My PDK is  ti-processor-sdk-rtos-j721e-evm-07_01_00_11/pdk_jacinto_07_01_00_45 

And  I change  DISP_APP_TEST_EDP to 1U ，Nothing else has changed。

I am using CCS to debug the demo ,I have checked the display, but there is no display, no DP signal can be detected。

and Uart show no error ，

I have saw DP need DP0_PWR_SW_EN  set High ， but I dont see any code to set it .

Hi jie xu,

Are you using Display port0 on the EVM? Can you please confirm? 

I am also trying same on EVM, will get back to you.

Regards,

Brijesh

hi  Brijesh Jadav

yes, i am using the display port0 on the evm and it dislay nomal on linux

Hi Jie Xu,

Can yo please apply attached patch on PDK and try with eDP output example? With this change, i am able to display on eDP.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/Dss_5F00_eDP_5F00_Fix.patch

Regards,

Brijesh

HI Brijesh,

Thanks for your replay ,

I patch the code ,Now it can Run and can display normal ,

Can you revise the reasons for these places？

Thanks again

Regards,

jie xu

Hi Jie Xu,

There was an issue in the clock source settings, which is fixed in the patch.

Please close this thread, if you think the question is answered. 

Regards,

Brijesh