AM6548: GPIO interrupt routing problem

Ruediger Wurth

Part Number: AM6548

Dear experts,

We are working with AM6548 at our custom board using RTOS SDK6.03. We did not yet migrate to SDK7.
Now I want to generate a GPIO interrupt for GPIO0_63 at the A53 core where TI-RTOS is running.

Therefore I studied the 'main_led_blink" example, but that uses a WKUP_GPIO:
In GPIO_configIntRouter() it substitues the whole GPIO0_BASE with the CSL_WKUP_GPIO0_BASE:

/* no main domain GPIO pins directly connected to LEDs on GP EVM,
use WKUP domain GPIO pins which connected to LEDs on base board */
cfg->baseAddr = CSL_WKUP_GPIO0_BASE;

For sure that's not what I need.

In addition I studied this E2E post:
https://e2e.ti.com/support/processors/f/791/t/959349 PROCESSOR-SDK-DRA8X-TDA4X: GPIO interrupt
where GPIO0_97 to MCU2_0 on a DRA8X-TDA4X is used.
But this also didn't help much, because I have a AM6548.

My current situation is that I configured the GPIO as interrupt input:

GPIO_INTSTAT23 at address 0x60005C changes from 0x00000000 to 0x80000000 an the first GPIO value change.
So I can see that the interrupt flag register is set.
So far so good.

But I get no interrupt callback at the A53 core.
Main issue is that interrupt routing doesn't work:
In PDK\ti\drv\gpio\soc\am65xx\GPIO_soc.c in function GPIO_socConfigIntrPath() the call to Sciclient_rmIrqSet() always returns -1

I tried several IRQ numbers (dst_host_irq=395 should be the correct one):

Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=392...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=393...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=394...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=395...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=396...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=397...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=398...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=399...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=400...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=401...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=402...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=403...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=404...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=405...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=406...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=407...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=408...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=409...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=410...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=411...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=412...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=413...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=414...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=415...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=416...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=417...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=418...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=419...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=420...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=421...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=422...FAILED: -1
Sciclient_rmIrqSet() src_id=57 src_index=259 dst_id=56 dst_host_irq=423...FAILED: -1

What can I do?
Which rmIrqReq.dst_host_irq can I use?

Regards,
Ruediger

over 3 years ago

0 Sunita Nadampalli over 3 years ago

TI__Expert 5970 points

Hi Ruediger,

Thanks for your patience! The interrupt routing at sciclient works based on the interrupt ranges assigned for each core in the board config file.

The actual interrupt number for a peripheral on a given core needs to be picked up from the above mentioned range.

In TI SDK, the default board cfg is located at:

/pdk/packages/ti/drv/sciclient/soc/Vx/sciclient_defaultBoardcfg_rm.c

Please share the board config file you have defined for your HW/SW codebase.

We can review and provide feedback on which number to be picked for GPIO.

Thanks & Regards,

Sunita.

0 Ruediger Wurth over 3 years ago in reply to Sunita Nadampalli

Intellectual 705 points

Sunita,

I checked now the file in our PDK:

PDK/packages/ti/drv/sciclient/soc/Vx/sciclient_defaultBoardcfg_rm.c

        {
            .start_resource = 392,
            .num_resource = 32,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_GIC_IRQ,
                         TISCI_RESASG_SUBTYPE_GIC_IRQ_MAIN_GPIO),
            .host_id = TISCI_HOST_ID_ALL,
        },

PDK/packages/ti/drv/sciclient/soc/Vx/sciclient_defaultBoardcfg_rm_sr2.c

        {
            .num_resource = 32U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_GIC0, TISCI_RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
            .start_resource = 392U,
            .host_id = TISCI_HOST_ID_ALL,
        },

It seems to me, the range 392 ... 423 is correct.

sciclient_defaultBoardcfg_rm.c

/*
 * Copyright (c) 2018-2020, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
/**
 *  \file V0/sciclient_defaultBoardcfg.c
 *
 *  \brief File containing the boardcfg default data structure to
 *      send TISCI_MSG_BOARD_CONFIG message.
 *
 */
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

#include <ti/drv/sciclient/soc/sysfw/include/am65x/tisci_hosts.h>
#include <ti/drv/sciclient/soc/sysfw/include/am65x/tisci_boardcfg_constraints.h>
#include <ti/drv/sciclient/soc/V0/sciclient_defaultBoardcfg.h>

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

#if defined (BUILD_MCU1_0)
const struct tisci_local_rm_boardcfg gBoardConfigLow_rm
__attribute__(( aligned(128), section(".boardcfg_data") )) =
{
    .rm_boardcfg = {
        /* tisci_boardcfg_abi_rev */
        .rev = {
            .tisci_boardcfg_abi_maj = TISCI_BOARDCFG_RM_ABI_MAJ_VALUE,
            .tisci_boardcfg_abi_min = TISCI_BOARDCFG_RM_ABI_MIN_VALUE,
        },
        .host_cfg = {
            .subhdr = {
                .magic = TISCI_BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
                .size  = sizeof(struct tisci_boardcfg_rm_host_cfg),
            },
            /* For now allowing all the atypes, QoS, orderId and priority */
            .host_cfg_entries = {
             [0] = {
                    /* Allowed atype configuration for the host ID. The host ID
                     * gets assigned a list of atypes which are allowed. atype
                     * is a 2-bit field with 3 possible values. Thus in one
                     * 8-bit word, flags are set specifying whether or not an
                     * atype value is allowed for the host ID. For each atype,
                     * the value of 01b means not allowed, 10b means allowed,
                     * and 11b and 00b are invalid/errors. These are encoded in
                     * a bitfield because there is one set of allowed atypes
                     * for every host ID.
                     */
                    .allowed_atype = 0b101010,
                    /* Allowed QoS level configuration for host ID. The host
                     * ID gets assigned a list of QoS levels which are allowed.
                     * As QoS level is a 3-bit field, there are 8 possible
                     * order-IDs. Thus in one 16-bit word, flags are set
                     * specifying whether or not the QoS level is allowed for
                     * the host ID. For each QoS level, the value of 01b means
                     * not allowed, 10b means allowed, and 11b and 00b are
                     * invalid/errors. These are encoded in a bitfield because
                     * there is one set of allowed QoS levels for every host ID.
                     */
                    .allowed_qos   = 0xAAAA,
                    /* Allowed order-ID configuration for the host ID. The host
                     * ID gets assigned a list of order-IDs which are allowed.
                     * As order-ID is a 4-bit field, there are 16 possible
                     * order-IDs. Thus in one 32-bit word, flags are set
                     * specifying whether or not the order-ID is allowed for
                     * the host ID. For each order-ID, the value of 01b means
                     * not allowed, 10b means allowed, and 11b and 00b are
                     * invalid/errors. These are encoded in a bitfield because
                     * there is one set of allowed order-IDs for every host ID.
                     */
                    .allowed_orderid = 0xAAAAAAAA,
                    /* Allowed bus priority configuration for host ID. The host
                     * ID gets assigned a list of bus priorities which are
                     * allowed. As bus priority is a 3-bit field, there are 8
                     * possible bus priorities. Thus in one 16-bit word, flags
                     * are set specifying whether or not the bus priority is
                     * allowed for the host ID. For each bus priority, the
                     * value of 01b means not allowed, 10b means allowed, and
                     * 11b and 00b are invalid/errors. These are encoded in a
                     * bitfield because there is one set of allowed bus
                     * priorities for every host ID.
                     */
                    .allowed_priority = 0xAAAA,
                    /* Allowed UDMAP channel scheduling priority configuration
                     * for host ID. The host ID gets assigned a list of UDMAP
                     * channel scheduling priorities which are allowed. As
                     * UDMAP channel scheduling priority is a 2-bit field,
                     * there are 4 possible UDMAP channel scheduling priorities.
                     * Thus in one 8-bit word, flags are set specifying whether
                     * or not UDMAP channel scheduling priority is allowed for
                     * the host ID. For each priority, the value of 01b means
                     * not allowed, 10b means allowed, and 11b and 00b are
                     * invalid/errors. These are encoded in a bitfield because
                     * there is one set of allowed UDMAP channel scheduling
                     * priorities for every host ID.
                     */
                    .allowed_sched_priority = 0xAA
                    },
                [1] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [2] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [3] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [4] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [5] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [6] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [7] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [8] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [9] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [10] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [11] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [12] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [13] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [14] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [15] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [16] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [17] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [18] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [19] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [20] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [21] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [22] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [23] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [24] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [25] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [26] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [27] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [28] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [29] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [30] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [31] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    }
            },
        },
        .resasg = {
            .subhdr = {
                .magic = TISCI_BOARDCFG_RM_RESASG_MAGIC_NUM,
                .size  = sizeof(struct tisci_boardcfg_rm_resasg),
            },
            .resasg_entries_size = TISCI_RESASG_UTYPE_CNT *
                    sizeof(struct tisci_boardcfg_rm_resasg_entry),
        },
    },
    .resasg_entries = {
        /* Refer to the AM65xx TRM Table 10-102. Global Event Map to make
         * sense of the following numbers.
         */
        {
            /* Main Nav UDMASS IA VINT 0 - 15 reserved for use by DMSC */
            .start_resource = 16,
            .num_resource = 240,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_UDMASS_IA0,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_VINT),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            /* MCU Nav UDMASS IA SEVI 0 - 15 reserved for use by DMSC */
            .start_resource = 16,
            .num_resource = 4592,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_UDMASS_IA0,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_SEVI),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 32768,
            .num_resource = 512,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_UDMASS_IA0,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_MEVI),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 36864,
            .num_resource = 512,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_UDMASS_IA0,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_UDMASS_IA0_GEVI),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 0,
            .num_resource = 64,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_MODSS_IA0,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_VINT),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 20480,
            .num_resource = 1024,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_MODSS_IA0,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_MODSS_IA0_SEVI),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 0,
            .num_resource = 64,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_MODSS_IA1,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_VINT),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 22528,
            .num_resource = 1024,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_MODSS_IA1,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_MODSS_IA1_SEVI),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 43008,
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_MCRC,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_MCRC_LEVI),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 0,
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_UDMAP,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_UDMAP_GCFG),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 49152,
            .num_resource = 1024,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_UDMAP,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_UDMAP_TRIGGER),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            /* Main Nav UDMAP tx channel 0 reserved for use by DMSC */
            .start_resource = 1,
            .num_resource = 7,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_UDMAP,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_HCHAN),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 8,
            .num_resource = 112,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_UDMAP,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_CHAN),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 120,
            .num_resource = 32,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_UDMAP,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_UDMAP_TX_ECHAN),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            /* Main Nav UDMAP rx channel 0 - 1 reserved for use by DMSC */
            .start_resource = 2,
            .num_resource = 6,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_UDMAP,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_HCHAN),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 8,
            .num_resource = 142,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_UDMAP,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_CHAN),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 150,
            .num_resource = 150,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_UDMAP,
                    TISCI_RESASG_SUBTYPE_MAIN_NAV_UDMAP_RX_FLOW_COMMON),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 0,
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_UDMAP,
                    TISCI_RESASG_SUBTYPE_MAIN_NAV_UDMAP_INVALID_FLOW_OES),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            /* Ring 0 is reserved for use by DMSC */
            .start_resource = 1,
            .num_resource = 151,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_RA,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_TX),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            /* Ring 152 is reserved for use by DMSC */
            .start_resource = 153,
            .num_resource = 149,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_RA,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_RA_RING_UDMAP_RX),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            /* Rings 302 and 303 are reserved for use by DMSC */
            .start_resource = 304,
            .num_resource = 464,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_RA,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_RA_RING_GP),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 0,
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_RA,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_RA_ERROR_OES),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 1024,
            .num_resource = 1024,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_RA,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_RA_VIRTID),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 0,
            .num_resource = 32,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_RA,
                         TISCI_RESASG_SUBTYPE_MAIN_NAV_RA_MONITOR),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            /* MCU Nav UDMASS IA VINT 0 - 7 reserved for use by DMSC */
            .start_resource = 8,
            .num_resource = 248,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_UDMASS_IA0,
                         TISCI_RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_VINT),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            /* MCU Nav UDMASS IA SEVI 16384 - 16391 reserved for use by DMSC */
            .start_resource = 16392,
            .num_resource = 1000,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_UDMASS_IA0,
                         TISCI_RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_SEVI),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 17392,
            .num_resource = 528,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_UDMASS_IA0,
                         TISCI_RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_SEVI),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 34816,
            .num_resource = 128,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_UDMASS_IA0,
                         TISCI_RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_MEVI),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 39936,
            .num_resource = 256,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_UDMASS_IA0,
                         TISCI_RESASG_SUBTYPE_MCU_NAV_UDMASS_IA0_GEVI),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 43136,
            .num_resource = 4,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_MCRC,
                         TISCI_RESASG_SUBTYPE_MCU_NAV_MCRC_LEVI),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 0,
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_UDMAP,
                         TISCI_RESASG_SUBTYPE_MCU_NAV_UDMAP_GCFG),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 56320,
            .num_resource = 256,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_UDMAP,
                         TISCI_RESASG_SUBTYPE_MCU_NAV_UDMAP_TRIGGER),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 0,
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_UDMAP,
                         TISCI_RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_HCHAN),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 2,
            .num_resource = 46,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_UDMAP,
                         TISCI_RESASG_SUBTYPE_MCU_NAV_UDMAP_TX_CHAN),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 0,
            .num_resource = 2,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_UDMAP,
                         TISCI_RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_HCHAN),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 2,
            .num_resource = 46,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_UDMAP,
                         TISCI_RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_CHAN),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 48,
            .num_resource = 48,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_UDMAP,
                    TISCI_RESASG_SUBTYPE_MCU_NAV_UDMAP_RX_FLOW_COMMON),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 0,
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_UDMAP,
                    TISCI_RESASG_SUBTYPE_MCU_NAV_UDMAP_INVALID_FLOW_OES),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 61440,
            .num_resource = 64,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MSMC,
                         TISCI_RESASG_SUBTYPE_MSMC_DRU),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 0,
            .num_resource = 48,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_RA,
                         TISCI_RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_TX),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 48,
            .num_resource = 48,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_RA,
                         TISCI_RESASG_SUBTYPE_MCU_NAV_RA_RING_UDMAP_RX),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 96,
            .num_resource = 160,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_RA,
                         TISCI_RESASG_SUBTYPE_MCU_NAV_RA_RING_GP),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 0,
            .num_resource = 1,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_RA,
                         TISCI_RESASG_SUBTYPE_MCU_NAV_RA_ERROR_OES),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 2048,
            .num_resource = 1024,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_RA,
                         TISCI_RESASG_SUBTYPE_MCU_NAV_RA_VIRTID),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 0,
            .num_resource = 32,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_RA,
                         TISCI_RESASG_SUBTYPE_MCU_NAV_RA_MONITOR),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            /* Proxy 0 reserved for use by DMSC */
            .start_resource = 1U,
            .num_resource = 63U,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MAIN_NAV_PROXY, TISCI_RESASG_SUBTYPE_MAIN_NAV_PROXY_PROXIES),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 0U,
            .num_resource = 64U,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_MCU_NAV_PROXY, TISCI_RESASG_SUBTYPE_MCU_NAV_PROXY_PROXIES),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            /* GIC inputs 64 - 79 reserved for use by DMSC */
            .start_resource = 80,
            .num_resource = 48,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_GIC_IRQ,
                         TISCI_RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET0),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 392,
            .num_resource = 32,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_GIC_IRQ,
                         TISCI_RESASG_SUBTYPE_GIC_IRQ_MAIN_GPIO),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 498,
            .num_resource = 6,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_GIC_IRQ,
                         TISCI_RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET1),
            .host_id = TISCI_HOST_ID_A53_0,
        },
        {
            .start_resource = 448,
            .num_resource = 50,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_GIC_IRQ,
                         TISCI_RESASG_SUBTYPE_GIC_IRQ_MAIN_NAV_SET1),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 544,
            .num_resource = 16,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_GIC_IRQ,
                         TISCI_RESASG_SUBTYPE_GIC_IRQ_COMP_EVT),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 712,
            .num_resource = 16,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_GIC_IRQ,
                         TISCI_RESASG_SUBTYPE_GIC_IRQ_WKUP_GPIO),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            /* VIM inputs 64 - 67 reserved for use by DMSC */
            .start_resource = 68,
            .num_resource = 28,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_PULSAR_C0_IRQ,
                         TISCI_RESASG_SUBTYPE_PULSAR_C0_IRQ_MCU_NAV),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 124,
            .num_resource = 16,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_PULSAR_C0_IRQ,
                         TISCI_RESASG_SUBTYPE_PULSAR_C0_IRQ_WKUP_GPIO),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 160,
            .num_resource = 32,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_PULSAR_C0_IRQ,
                         TISCI_RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_LVL),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 224,
            .num_resource = 48,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_PULSAR_C0_IRQ,
                         TISCI_RESASG_SUBTYPE_PULSAR_C0_IRQ_MAIN2MCU_PLS),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            /* VIM inputs 64 - 67 reserved for use by DMSC */
            .start_resource = 68,
            .num_resource = 28,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_PULSAR_C1_IRQ,
                         TISCI_RESASG_SUBTYPE_PULSAR_C1_IRQ_MCU_NAV),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 124,
            .num_resource = 16,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_PULSAR_C1_IRQ,
                         TISCI_RESASG_SUBTYPE_PULSAR_C1_IRQ_WKUP_GPIO),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 192,
            .num_resource = 32,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_PULSAR_C1_IRQ,
                         TISCI_RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_LVL),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 224,
            .num_resource = 48,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_PULSAR_C1_IRQ,
                         TISCI_RESASG_SUBTYPE_PULSAR_C1_IRQ_MAIN2MCU_PLS),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 46,
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_ICSSG0_IRQ,
                         TISCI_RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_NAV),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 88,
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_ICSSG0_IRQ,
                         TISCI_RESASG_SUBTYPE_ICSSG0_IRQ_MAIN_GPIO),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 46,
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_ICSSG1_IRQ,
                         TISCI_RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_NAV),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 88,
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_ICSSG1_IRQ,
                         TISCI_RESASG_SUBTYPE_ICSSG1_IRQ_MAIN_GPIO),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 46,
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_ICSSG2_IRQ,
                         TISCI_RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_NAV),
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .start_resource = 88,
            .num_resource = 8,
            .type = TISCI_RESASG_UTYPE(TISCI_RESASG_TYPE_ICSSG2_IRQ,
                         TISCI_RESASG_SUBTYPE_ICSSG2_IRQ_MAIN_GPIO),
            .host_id = TISCI_HOST_ID_ALL,
        },
    },
};
#endif

sciclient_defaultBoardcfg_rm_sr2.c

/*
 * Copyright (c) 2018-2020, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
/**
 *  \file V0/sciclient_defaultBoardcfg_sr2.c
 *
 *  \brief File containing the boardcfg default data structure to
 *      send TISCI_MSG_BOARD_CONFIG message.
 *
 */
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */

#include <ti/drv/sciclient/soc/sysfw/include/am65x/tisci_hosts.h>
#include <ti/drv/sciclient/soc/sysfw/include/am65x/tisci_boardcfg_constraints.h>
#include <ti/drv/sciclient/soc/V0/sciclient_defaultBoardcfg.h>

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

#if defined (BUILD_MCU1_0)
const struct tisci_local_rm_boardcfg gSciclient_boardCfgLow_rm_sr2
__attribute__(( aligned(128), section(".boardcfg_data") )) =
{
    .rm_boardcfg = {
        /* tisci_boardcfg_abi_rev */
        .rev = {
            .tisci_boardcfg_abi_maj = TISCI_BOARDCFG_RM_ABI_MAJ_VALUE,
            .tisci_boardcfg_abi_min = TISCI_BOARDCFG_RM_ABI_MIN_VALUE,
        },
        .host_cfg = {
            .subhdr = {
                .magic = TISCI_BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
                .size  = sizeof(struct tisci_boardcfg_rm_host_cfg),
            },
            /* For now allowing all the atypes, QoS, orderId and priority */
            .host_cfg_entries = {
             [0] = {
                    /* Allowed atype configuration for the host ID. The host ID
                     * gets assigned a list of atypes which are allowed. atype
                     * is a 2-bit field with 3 possible values. Thus in one
                     * 8-bit word, flags are set specifying whether or not an
                     * atype value is allowed for the host ID. For each atype,
                     * the value of 01b means not allowed, 10b means allowed,
                     * and 11b and 00b are invalid/errors. These are encoded in
                     * a bitfield because there is one set of allowed atypes
                     * for every host ID.
                     */
                    .allowed_atype = 0b101010,
                    /* Allowed QoS level configuration for host ID. The host
                     * ID gets assigned a list of QoS levels which are allowed.
                     * As QoS level is a 3-bit field, there are 8 possible
                     * order-IDs. Thus in one 16-bit word, flags are set
                     * specifying whether or not the QoS level is allowed for
                     * the host ID. For each QoS level, the value of 01b means
                     * not allowed, 10b means allowed, and 11b and 00b are
                     * invalid/errors. These are encoded in a bitfield because
                     * there is one set of allowed QoS levels for every host ID.
                     */
                    .allowed_qos   = 0xAAAA,
                    /* Allowed order-ID configuration for the host ID. The host
                     * ID gets assigned a list of order-IDs which are allowed.
                     * As order-ID is a 4-bit field, there are 16 possible
                     * order-IDs. Thus in one 32-bit word, flags are set
                     * specifying whether or not the order-ID is allowed for
                     * the host ID. For each order-ID, the value of 01b means
                     * not allowed, 10b means allowed, and 11b and 00b are
                     * invalid/errors. These are encoded in a bitfield because
                     * there is one set of allowed order-IDs for every host ID.
                     */
                    .allowed_orderid = 0xAAAAAAAA,
                    /* Allowed bus priority configuration for host ID. The host
                     * ID gets assigned a list of bus priorities which are
                     * allowed. As bus priority is a 3-bit field, there are 8
                     * possible bus priorities. Thus in one 16-bit word, flags
                     * are set specifying whether or not the bus priority is
                     * allowed for the host ID. For each bus priority, the
                     * value of 01b means not allowed, 10b means allowed, and
                     * 11b and 00b are invalid/errors. These are encoded in a
                     * bitfield because there is one set of allowed bus
                     * priorities for every host ID.
                     */
                    .allowed_priority = 0xAAAA,
                    /* Allowed UDMAP channel scheduling priority configuration
                     * for host ID. The host ID gets assigned a list of UDMAP
                     * channel scheduling priorities which are allowed. As
                     * UDMAP channel scheduling priority is a 2-bit field,
                     * there are 4 possible UDMAP channel scheduling priorities.
                     * Thus in one 8-bit word, flags are set specifying whether
                     * or not UDMAP channel scheduling priority is allowed for
                     * the host ID. For each priority, the value of 01b means
                     * not allowed, 10b means allowed, and 11b and 00b are
                     * invalid/errors. These are encoded in a bitfield because
                     * there is one set of allowed UDMAP channel scheduling
                     * priorities for every host ID.
                     */
                    .allowed_sched_priority = 0xAA
                    },
                [1] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [2] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [3] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [4] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [5] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [6] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [7] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [8] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [9] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [10] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [11] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [12] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [13] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [14] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [15] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [16] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [17] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [18] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [19] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [20] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [21] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [22] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [23] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [24] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [25] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [26] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [27] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [28] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [29] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [30] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    },
                [31] = {
                        .allowed_atype = 0b101010,
                        .allowed_qos   = 0xAAAA,
                        .allowed_orderid = 0xAAAAAAAA,
                        .allowed_priority = 0xAAAA,
                        .allowed_sched_priority = 0xAA
                    }
            },
        },
        .resasg = {
            .subhdr = {
                .magic = TISCI_BOARDCFG_RM_RESASG_MAGIC_NUM,
                .size  = sizeof(struct tisci_boardcfg_rm_resasg),
            },
            .resasg_entries_size = TISCI_RESASG_UTYPE_CNT_SR2 *
                    sizeof(struct tisci_boardcfg_rm_resasg_entry),
        },
    },
.resasg_entries = {
        {
            .num_resource = 1024,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_MODSS_INTA0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
            .start_resource = 20480,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 64U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_MODSS_INTA0, TISCI_RESASG_SUBTYPE_IA_VINT),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1024,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_MODSS_INTA1, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
            .start_resource = 22528,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 64U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_MODSS_INTA1, TISCI_RESASG_SUBTYPE_IA_VINT),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 4592,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_UDMASS_INTA0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
            .start_resource = 16,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 240U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_UDMASS_INTA0, TISCI_RESASG_SUBTYPE_IA_VINT),
            .start_resource = 16U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1528,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_INTR_AGGR_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
            .start_resource = 16392,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 248U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_INTR_AGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT),
            .start_resource = 8U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 28U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_ARMSS0_CPU1, TISCI_RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0),
            .start_resource = 68U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 16U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_ARMSS0_CPU1, TISCI_RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0),
            .start_resource = 124U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 32U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_ARMSS0_CPU1, TISCI_RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0),
            .start_resource = 192U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 48U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_ARMSS0_CPU1, TISCI_RESASG_SUBTYPE_MCU_ARMSS0_CPU1_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0),
            .start_resource = 224U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 48U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_GIC0, TISCI_RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
            .start_resource = 80U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 32U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_GIC0, TISCI_RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
            .start_resource = 392U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 56U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_GIC0, TISCI_RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP1_FROM_NAVSS0_INTR_ROUTER_0),
            .start_resource = 448U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 16U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_GIC0, TISCI_RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0),
            .start_resource = 544U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 16U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_GIC0, TISCI_RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0),
            .start_resource = 712U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 28U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_ARMSS0_CPU0, TISCI_RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MCU_NAVSS0_INTR_ROUTER_0),
            .start_resource = 68U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 16U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_ARMSS0_CPU0, TISCI_RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0),
            .start_resource = 124U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 32U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_ARMSS0_CPU0, TISCI_RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_LVL_INTRTR0),
            .start_resource = 160U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 48U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_ARMSS0_CPU0, TISCI_RESASG_SUBTYPE_MCU_ARMSS0_CPU0_INTR_IRQ_GROUP0_FROM_MAIN2MCU_PLS_INTRTR0),
            .start_resource = 224U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0, TISCI_RESASG_SUBTYPE_NAVSS0_CPTS0_HW1_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0, TISCI_RESASG_SUBTYPE_NAVSS0_CPTS0_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 1U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0, TISCI_RESASG_SUBTYPE_NAVSS0_CPTS0_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 2U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0, TISCI_RESASG_SUBTYPE_NAVSS0_CPTS0_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 3U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0, TISCI_RESASG_SUBTYPE_NAVSS0_CPTS0_HW5_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 4U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0, TISCI_RESASG_SUBTYPE_NAVSS0_CPTS0_HW6_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 5U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0, TISCI_RESASG_SUBTYPE_NAVSS0_CPTS0_HW7_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 6U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0, TISCI_RESASG_SUBTYPE_NAVSS0_CPTS0_HW8_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 7U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 8U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_ESM0, TISCI_RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT0_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
            .start_resource = 248U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 8U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_ESM0, TISCI_RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT1_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
            .start_resource = 256U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 8U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_ESM0, TISCI_RESASG_SUBTYPE_ESM0_ESM_PLS_EVENT2_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
            .start_resource = 264U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 8U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PDMA1, TISCI_RESASG_SUBTYPE_PDMA1_LEVENT_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 8U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PDMA1, TISCI_RESASG_SUBTYPE_PDMA1_LEVENT_IN_IRQ_GROUP0_FROM_CMPEVENT_INTRTR0),
            .start_resource = 8U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 1U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 2U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 3U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 6U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
            .start_resource = 4U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 6U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
            .start_resource = 10U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 8U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
            .start_resource = 46U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 8U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
            .start_resource = 88U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_CPSW0, TISCI_RESASG_SUBTYPE_MCU_CPSW0_CPTS_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_CPSW0, TISCI_RESASG_SUBTYPE_MCU_CPSW0_CPTS_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 1U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG2, TISCI_RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG2, TISCI_RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 1U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG2, TISCI_RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 2U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG2, TISCI_RESASG_SUBTYPE_PRU_ICSSG2_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 3U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 6U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG2, TISCI_RESASG_SUBTYPE_PRU_ICSSG2_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
            .start_resource = 4U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 6U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG2, TISCI_RESASG_SUBTYPE_PRU_ICSSG2_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
            .start_resource = 10U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 8U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG2, TISCI_RESASG_SUBTYPE_PRU_ICSSG2_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
            .start_resource = 46U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 8U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG2, TISCI_RESASG_SUBTYPE_PRU_ICSSG2_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
            .start_resource = 88U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 8U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_WKUP_ESM0, TISCI_RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT0_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0),
            .start_resource = 88U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 8U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_WKUP_ESM0, TISCI_RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT1_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0),
            .start_resource = 96U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 8U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_WKUP_ESM0, TISCI_RESASG_SUBTYPE_WKUP_ESM0_ESM_PLS_EVENT2_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0),
            .start_resource = 104U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 12U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_WKUP_DMSC0_CORTEX_M3_0, TISCI_RESASG_SUBTYPE_WKUP_DMSC0_CORTEX_M3_0_NVIC_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0),
            .start_resource = 184U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PCIE0, TISCI_RESASG_SUBTYPE_PCIE0_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PCIE1, TISCI_RESASG_SUBTYPE_PCIE1_PCIE_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 1U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 2U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_INTRTR0),
            .start_resource = 3U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 6U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
            .start_resource = 4U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 6U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
            .start_resource = 10U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 8U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_NAVSS0_INTR_ROUTER_0),
            .start_resource = 46U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 8U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_SLV_INTR_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0),
            .start_resource = 88U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 63U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_PROXY0, TISCI_RESASG_SUBTYPE_PROXY_PROXIES),
            .start_resource = 1U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 64U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_PROXY0, TISCI_RESASG_SUBTYPE_PROXY_PROXIES),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 7U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX_H),
            .start_resource = 1U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 112U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
            .start_resource = 8U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 32U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX_EXT),
            .start_resource = 120U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 7U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX_H),
            .start_resource = 153U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 142U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
            .start_resource = 160U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 464U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_GP),
            .start_resource = 304U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 2U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX_H),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 46U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_TX),
            .start_resource = 2U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 2U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX_H),
            .start_resource = 48U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 46U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_UDMAP_RX),
            .start_resource = 50U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 160U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_GP),
            .start_resource = 96U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_ERROR_OES),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 64U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_VIRTID),
            .start_resource = 64U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 32U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_ERROR_OES),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 64U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_VIRTID),
            .start_resource = 128U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 32U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_RINGACC0, TISCI_RESASG_SUBTYPE_RA_MONITORS),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 7U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_UDMAP0, TISCI_RESASG_SUBTYPE_UDMAP_TX_HCHAN),
            .start_resource = 1U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 112U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_UDMAP0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 8U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 32U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_UDMAP0, TISCI_RESASG_SUBTYPE_UDMAP_TX_ECHAN),
            .start_resource = 120U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 6U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_UDMAP0, TISCI_RESASG_SUBTYPE_UDMAP_RX_HCHAN),
            .start_resource = 2U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 142U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_UDMAP0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 8U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1024U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_UDMAP0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
            .start_resource = 49152U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 2U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_UDMAP0, TISCI_RESASG_SUBTYPE_UDMAP_TX_HCHAN),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 46U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_UDMAP0, TISCI_RESASG_SUBTYPE_UDMAP_TX_CHAN),
            .start_resource = 2U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 2U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_UDMAP0, TISCI_RESASG_SUBTYPE_UDMAP_RX_HCHAN),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 46U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_UDMAP0, TISCI_RESASG_SUBTYPE_UDMAP_RX_CHAN),
            .start_resource = 2U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 256U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_UDMAP0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
            .start_resource = 56320U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 150U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_UDMAP0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
            .start_resource = 150U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_UDMAP0, TISCI_RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_NAVSS0_UDMAP0, TISCI_RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 48U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_UDMAP0, TISCI_RESASG_SUBTYPE_UDMAP_RX_FLOW_COMMON),
            .start_resource = 48U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_UDMAP0, TISCI_RESASG_SUBTYPE_UDMAP_INVALID_FLOW_OES),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
        {
            .num_resource = 1U,
            .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_NAVSS0_UDMAP0, TISCI_RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
            .start_resource = 0U,
            .host_id = TISCI_HOST_ID_ALL,
        },
    },
};
#endif

In the newest version of this file at TI git, it has been consolidated and values changed:
https://git.ti.com/cgit/processor-sdk/pdk/log/packages/ti/drv/sciclient/soc/V0/sciclient_defaultBoardcfg_rm.c
But we use definitively Processor-SDK-RTOS-AM65xx V6.03 with pdk_am65xx_1_0_7

Regards,
Ruediger

0 Sunita Nadampalli over 3 years ago in reply to Ruediger Wurth

TI__Expert 5970 points

Hi Ruediger,

Thanks, I will review the config files and check if anything is missing in your configuration.

Thanks & Regards,

Sunita.

0 Sunita Nadampalli over 3 years ago in reply to Sunita Nadampalli

TI__Expert 5970 points

Hi Ruediger,

Please share the below configuration from your application/code wherever you are setting up the interrupt router configuration:

rmIrqReq.valid_params =
rmIrqReq.valid_params |=
rmIrqReq.src_id =
rmIrqReq.global_event =
rmIrqReq.src_index =
rmIrqReq.dst_id =
rmIrqReq.dst_host_irq =

rmIrqReq.ia_id =
rmIrqReq.vint =
rmIrqReq.vint_status_bit_index =
rmIrqReq.secondary_host =
retVal = Sciclient_rmIrqSet(
&rmIrqReq, &rmIrqResp, APP_SCICLIENT_TIMEOUT);

Thanks & Regards,

Sunita.

0 Ruediger Wurth over 3 years ago in reply to Sunita Nadampalli

Intellectual 705 points

Hello Sunita,
thanks for keeping up.

Here my code taken from PDK\ti\drv\gpio\soc\am65xx\GPIO_soc.c
function GPIO_socConfigIntrPath()

I put the real values below and the original marcos as comments.

    memset (&rmIrqReq,0,sizeof(rmIrqReq));

    rmIrqReq.secondary_host = 0xFFu; // TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST
    rmIrqReq.src_id    = 57;         // TISCI_DEV_GPIO0
    rmIrqReq.src_index = 259;  // 256 + bankNum;  /* This is the bus_gpio_bank (256-261) mentioned in DMSC firmware guide  for AM6_DEV_GPIO0 */
                               //       bankNum = pinNum/16; /* Each GPIO bank has 16 pins */

    /* Set the destination interrupt */ 
    rmIrqReq.valid_params |= (1u << 0u); // TISCI_MSG_VALUE_RM_DST_ID_VALID;
    rmIrqReq.valid_params |= (1u << 1u); // TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;

    /* Set the destination based on the core */
    rmIrqReq.dst_id       = 56;  // TISCI_DEV_GIC0
    rmIrqReq.dst_host_irq = dst_host_irq;  // 392 ... 423

    UART_printf("Sciclient_rmIrqSet() src_id=%d src_index=%d dst_id=%d dst_host_irq=%d...", src_id, src_index, dst_id, dst_host_irq);

    retVal = Sciclient_rmIrqSet( (const struct tisci_msg_rm_irq_set_req *)&rmIrqReq, &rmIrqResp, SCICLIENT_SERVICE_WAIT_FOREVER);
                 
    if(retVal==CSL_PASS) {
        UART_printf("OK\n");
    } else {
        UART_printf("FAILED: %d\n", retVal);
    }

Please note that I listed the output of the UART_printf() in one of my posts before.
For 'src_index' I also tried different values, without success.

Best regards,
Ruediger

0 Sunita Nadampalli over 3 years ago in reply to Ruediger Wurth

TI__Expert 5970 points

Hi Ruediger,

Please ensure

1. the default SDK GPIO example (with WKUP GPIO) is functional

2. the interrupt range assigned for A53 core is not taken up by other application on A53.

Thanks & Regards,

Sunita.

0 Ruediger Wurth over 3 years ago in reply to Sunita Nadampalli

Intellectual 705 points

Hello Sunita,

now I did the following:

I converted the example program “PDK_1_0_7\packages\ti\drv\gpio\test\led_blink\” into a CCS project, which I attached here.
I modified the main_led_blink.c so that the interrupt-occured flag ‘gpio_intr_triggered’ is now a counter and prints the counter value in the main loop
This proves if the interrupt is really working or not: each GPIO interrupt increments the counter
I added the function Sciclient_rmGetResourceRange() to the main_led_blink.c to see which available IRQ resources it shows.

RESULTS

Running this example on an IDK board with CCS9.2 using the GEL-Files coming with CCS9.2 for debugging:

Sciclient_rmGetResourceRange() returns always 0 at the IDK board
The GPIO interrupt itself works well at the IDK board

UART output is

TISCI_RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0:
Type: 56, Subtype : 1, Start: 0, Num: 0
 
TISCI_RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0:
Type: 56, Subtype : 4, Start: 0, Num: 0
 
 
IntConfig:  portNum[0], pinNum[0], bankNum[0], intNum[712], eventId[0]
GPIO Led Blink Application
 
All tests have passed
irq-counter: 1
irq-counter: 1
irq-counter: 2
irq-counter: 2
irq-counter: 3
irq-counter: 3
irq-counter: 4

This shows that the function Sciclient_rmGetResourceRange() doesn’t work, but the GPIO interrupt itself is working in the example application.

Please, see attached ZIP file.
So I think using function Sciclient_rmGetResourceRange() leads us to a dead end.

Now I ran the same LED-example on our custom board (I loaded exactly the same out file via the JTAG debugger)

Result:

TISCI_RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0:
Type: 56, Subtype : 1, Start: 0, Num: 0
 
TISCI_RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0:
Type: 56, Subtype : 4, Start: 0, Num: 0
 
 
IntConfig:  portNum[0], pinNum[0], bankNum[0], intNum[712], eventId[0]
GPIO Led Blink Application
 
All tests have passed
irq-counter: 0
irq-counter: 0
irq-counter: 0
irq-counter: 0
irq-counter: 0
irq-counter: 0
irq-counter: 0
irq-counter: 0

So we can see that Sciclient_rmGetResourceRange() doesn’t work (like at IDK board), but the interrupt itself is also NOT working here!
So, why does the interrupt not work on our own board?

I think there are 2 main differences between running on IDK and running on our custom board:

IDK has a Sitara AM6548 SR1.0 and our board has a SR2.0 mounted
GEL files which are used for JTAG connection configure the DDR memory, load the SYSFW etc. are different between IDK and our custom board

So one next step would be to analyse possibility 1 (SR1 vs. SR2).
To try the example

either with an older custom board with SR1 (which I do not have here at home)
or with a IDK board which has a SR2 silicon. Do you have such a IDK board with SR2?

To analyse possibility 2 (GEL files difference), I run the example on our custom board (SR2) via sd-card by booting via SBL (not using JTAG).

Then no GEL files are used, just our SBL.

Result: It does also NOT work, the interrupt counter stays zero:

TISCI_RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0:
Type: 56, Subtype : 1, Start: 0, Num: 0
 
TISCI_RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0:
Type: 56, Subtype : 4, Start: 0, Num: 0
 
 
IntConfig:  portNum[0], pinNum[0], bankNum[0], intNum[712], eventId[0]
GPIO Led Blink Application
 
All tests have passed
irq-counter: 0
irq-counter: 0
irq-counter: 0
irq-counter: 0
irq-counter: 0
irq-counter: 0
irq-counter: 0
irq-counter: 0
irq-counter: 0

So my suspicion is now that the gpio irq routing does not work with silicon revision SR2.

Please, keep in mind that this LED example always says “All tests have passed”, even if the interrupt does not work.
This is really a lack in this example application.

Do you have any possibility to check the irq routing on a SR2 silicon?

Regards,
Ruediger

0 Ruediger Wurth over 3 years ago

Intellectual 705 points

Hi Sunita,

now I made a lot of tests, all with SDK6.3:
It turned out that the example program “PDK_1_0_7\packages\ti\drv\gpio\test\led_blink\”

Works well on a IDK board with SR1
Does NOT work on a IDK board with SR2 !!!

Now I am requesting from TI:

To let the “led_blink” example from PDK1.0.7 run on an SDK board with SR2
IMPORTANT: it is NOT enough just to prove the output of the original example, since that reports “All tests have passed” even if the interrupt is not triggered. This is a lack in the example program.
It is needed to modify the example program like I did in the attached ZIP file.
To find out why the function Sciclient_rmGetResourceRange() does not work at all when adding it in the “led_blink” example: not with IDK SR1 and not with IDK SR2
To find a workaround how we can route a GPIO interrupt with a SR2 silicon chip

As attachment I added here also the output of the modified led_blink example running on an IDK board with SR1 and on an IDK board with SR2.

Best regards,
Ruediger

(I was not able to attach any ZIP file here in this post, du to technical restrictions of the forum)

0 Karthik Ramanan over 2 years ago in reply to Ruediger Wurth

TI__Guru** 113800 points

Hi Ruediger,

Can you please try to attach the zip file here now?

The earlier issue that you faced was related to a glitch on the E2E system. Please reattempt now.

Regards

Karthik

0 Ruediger Wurth over 2 years ago in reply to Karthik Ramanan

Intellectual 705 points

Hello Karthik,
here is the zip file with the modified project.

led_example_extended.zip

Regards,
Ruediger

0 jian35385 over 2 years ago in reply to Ruediger Wurth

TI__Mastermind 23125 points

Ruediger,

just a sanity check, when you ran the example on the TI IDK, did you load the sysfw via CCS scripting console? you mentioned GEL file. Since sciclient calls required sysfw to be running, you will need to make sure the sysfw is running on the DMSC.

The standard practice of proceeding Sciclient_rmIrqSet() with Sciclient_rmGetResourceRange()

is the recommended procedure.

I assume you SBL does load sysfw, and also from the other thread, i assume you were already loading sysfw via CCS scripting console. but just wanted to double check.

regards

Jian

0 jian35385 over 2 years ago in reply to jian35385

TI__Mastermind 23125 points

ps. I build and ran your test code with SDK7.01 and got following messages on the UART window:

TISCI_RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_GPIOMUX_INTRTR0:
Type: 56, Subtype : 1, Start: 0, Num: 0

TISCI_RESASG_SUBTYPE_GIC0_SPI_IRQ_GROUP0_FROM_WKUP_GPIOMUX_INTRTR0:
Type: 56, Subtype : 4, Start: 0, Num: 0

IntConfig: portNum[0], pinNum[0], bankNum[0], intNum[712], eventId[0]

so it is not fully working for me either. I have SR2 EVM, so may be missing some hardware daughter cards.

Jian

0 Ruediger Wurth over 2 years ago in reply to jian35385

Intellectual 705 points

Jian,

to answer your question about sysfw load.
I used 2 different ways, both with the same result that interrupt routing did not work with a SR2 board:

when debugging, via javascript using PDK\ti\drv\sciclient\tools\ccsLoadDmsc\launch_am65xx.js
when booting via sdcard, using SBL which loads sysfw from sdcard

I wonder about this question, because I already write above at 2021-04-08 that interrupt routing works with SR1 but not with SR2.
A collegue has a new IDK board with SD2 and I have an old one with SR1.
We both tested with sd-card boot using the same SBL and app, but of course different sysfw (because SR1 vs. SR2).

In you post above you wrote that its also not working for you with your SR2 EVM.
I don't think that any missing daughter board has impact on GPIO interrupt routing via sysfw.

Regards, Ruediger

+1 jian35385 over 2 years ago in reply to Ruediger Wurth

TI__Mastermind 23125 points

Ruediger,

Our development team fix the issue and released the updated example in RTOS SDK 7.03:

https://www.ti.com/tool/download/PROCESSOR-SDK-RTOS-AM65X#release-notes

The root cause was due to hard-coded interrupt number and board config is different between SR1 and SR2.

Can you download the SDK and retest. I have not get a chance to test to release yet but want to inform you of the same.

regards

JIan

+1 Ruediger Wurth over 2 years ago in reply to jian35385

Intellectual 705 points

Jian,

I have currently no time to retest, but since TI is saying that they found the issue and fixed it I am confident that it works now with the new SDK.
Therefore we can close this topic.

Thank you, Ruediger

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AM6548: GPIO interrupt routing problem