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AM4378: Pixel rate calculation

Part Number: AM4378

Hi,

How to calculate  pixel rate mentioned in 13.1.1 DSS Features ?

Programmable pixel rate (up to 100 MHz)

www.ti.com.cn/.../spruhl7i.pdf

  • Hi Nancy,

    The DSS Pixel Rate is software programmable via the DISPC_DIVISOR register, which will divide said 100MHz clock as needed. The actual clock you're looking for is the DSS PCLK.

    Section "13.3.2.1.1.3 LCD Output and Data Format for the Parallel Interface" describes how PCLK cycles translate into pixel data for different types of displays. 

    So the formula you're looking for is Active_Horizontal_Pixels *  Active_Vertical_Pixels  * Refresh_Rate * (1 + Blanking Period %)  /  n = Pixel Clock, where the last "n" is the Pixels/ PCLK cycle as seen in Table 13-9, and the Blanking Period % is configurable.  

    Since something like an 8-bit Monochrome panel is able to display 8 pixels per PCLK cycle, you only need 1/8th the PCLK for the same display resolution.

    I would recommend looking at "13.5.2.5 Vertical and Horizontal Timings" to get a clearer example of how these parameters translate into LCD Timing and it's notes on the Blanking Period aka the "Pulse Width". 

    Please let me know if this has helped answer your question. 

    Best Regards,

    Andrei

  • Dear Aldea,

    Is there anyway to change the pix 100M  to  104M, because I want to test my lcd pannel(1600*900 @60hz), this pannel need 104M pixclock.  

  • The maximum supported pixel rate is 100MHz. Anything beyond is considered out of spec.