Dear Support,
Like in the other topic (https://e2e.ti.com/support/processors/f/processors-forum/985590/tda4vm-preprocess-padding-question), I have the same question with the TIDL module's output sizes.
All the tensors should be 120x160xN. all ioBufDesc->outPadX[0] values are zero, while the tensor sizes in some cases differ from the expected.
frame count: 8
input width: 640
input height: 480
output width: 160
output height: 120
channel number: 16
Output padding: 0 0 0 0-- Number of output buffers: 4
-- Buffer [0] scale: 8.000000
-- Buffer [1] scale: 16.000000
-- Buffer [2] scale: 2.000000
-- Buffer [3] scale: 8.000000
--Pushing tensor 0
--Pushing channel 0
Tensor sizes: 120 160 8
--Pushing tensor 1
--Pushing channel 0
Tensor sizes: 124 226 3
--Pushing tensor 2
--Pushing channel 0
Tensor sizes: 124 226 4
--Pushing tensor 3
--Pushing channel 0
Tensor sizes: 124 226 1
Currently we are using the data from these tensors that has the fitting size of our network's output. Is this difference ok to have there?
BR,
Gergely