• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 9 subscribers
  • Views 114 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TRF372017: Change the external CLK frequency setting

Ryan Lee TW
Intellectual 506 points
Part Number: TRF372017

Hi teams,

We want to use NXP Processor to control TRF372017, and let the Latch-Enable signal to notify TRF372017, as shown in the figure below:

But NXP Processor's SPI does not have a Latch-Enable Pin, is it possible to connect SPI CS to Latch-Enable and let CS (Always keep Hi, pull to Lo when data is to be transmitted) instead of Latch-Enable to transmit SPI data?

 Thanks.

  • 0
    TI__Guru 65954 points

    Hi Ryan,

    as long as you can configure the SPI CS pin to be logic low upon writing SPI DATA and SPI Clock, it will be fine. NXP processor need also need to ensure the setup/hold time described in Figure 1 and the timing specification table.

    -Kang