AFE7950EVM: TSW14J57EVM+AFE7950EVM: Applicatiom Software Development

Ganesh Kashyap B N

Part Number: AFE7950EVM
Other Parts Discussed in Thread: AFE7950, TSW14J57EVM,

Hello Team,

We are using AFE7950 in our project with Arria10 FPGA. Whereas the EVM and associated software serves the puropose of validating the ADC performance, we intend to modify a few things in the processing of FPGA to validate the end Application results.

In this regard, is it possible to share the FPGA source code for TSW14J57EVM working with AFE7950EVM ? This will help us to implement the application software.

Thanks

over 3 years ago

0 Vijayendra Varma Siddamsetty over 3 years ago

TI__Genius 10865 points

Hi Ganesh,

TSW14J57 source code is complex because it supports dynamic configuration for various devices/JESD modes and has HSDC Pro integration part. Because of this, it’s not useful to generate an FPGA design optimized for a particular JESD mode which is needed for your application.

We instead provide JESD reference designs based on TI JESD IP for this purpose. Currently we only have reference designs available with Xilinx platforms. You can request access to this at https://www.ti.com/tool/TI-JESD204-IP

Regards,

Vijay

0 Ganesh Kashyap B N over 3 years ago in reply to Vijayendra Varma Siddamsetty

Prodigy 20 points

Hi Vijay,

Thanks for the update. For some of our Internal reasons, we have to go with Arria 10 FPGA. Is there any other way out TI can help us in software Development ?

0 Vijayendra Varma Siddamsetty over 3 years ago in reply to Ganesh Kashyap B N

TI__Genius 10865 points

Hi Ganesh,

We already have reference designs for Xilinx platforms. We plan on supporting Intel FPGAs as well in future. I'm checking internally to align on timeline for this. I will get back to you.

Regards,

Vijay

+1 Vijayendra Varma Siddamsetty over 3 years ago in reply to Vijayendra Varma Siddamsetty

TI__Genius 10865 points

Hi Ganesh,

We have a reference design with Arria10 dev kit (https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-a10-gx-fpga.html) and AFE7444EVM. The same can be used as a reference and can updated for AFE79xxEVM by changing lane mapping and inversions accordingly.

You can access this design at below link:

https://tidrive.ext.ti.com/u/3F3ewxtd3szOXd7F/23e61366-7eb6-4c3f-9050-b7025e85372b?l

Regards,

Vijay

0 Ganesh Kashyap B N over 3 years ago in reply to Vijayendra Varma Siddamsetty

Prodigy 20 points

Hi Vijay,

Thanks for the update. Noted. Can you support us for choosing JESD Mode settings for TX/RX signal at 9.5GHz with a Signal Bandwidth of 20MHz ?

Can you share your Email ID for discussing further operational mode settings ?

0 Vijayendra Varma Siddamsetty over 3 years ago in reply to Ganesh Kashyap B N

TI__Genius 10865 points

Hi Ganesh,

I have your email ID. I will respond to you via email.

I will close this post. We can continue this discussion over the email chain.

Regards,

Vijay

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AFE7950EVM: TSW14J57EVM+AFE7950EVM: Applicatiom Software Development