Hi Team,
I am trying to simulate JESD interface between FPGA & AFE7900 in Hyperlynx.
Getting below error with IBIS Model. Please suggest solution.
Thanks
Dharma
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Hi Team,
I am trying to simulate JESD interface between FPGA & AFE7900 in Hyperlynx.
Getting below error with IBIS Model. Please suggest solution.
Thanks
Dharma
Hi Dharma,
As we already have an email thread regarding this issue, I replied to that.
We can continue discussion on that thread.
Regards,
Vijay