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DAC38RF82: DAC38rf82 cannot stably establish jesd204b and meet the problem of link configuration error

Tiewei Chen
Prodigy 20 points
Part Number: DAC38RF82
Other Parts Discussed in Thread: LMK04828

Hello,There

    We are now debugging DAC38RF82, In the mode LMFSHD=42111 ,meet the problem of elastic buffer match error.The first non-/k/ doesn't match "match_ctrl" and "match_data" programmed values.

 Design details:

(1)LMFSHD=42111;

(2)FDac(DACCLK)=4800M,External Diff Clk;

(3).Single DAC(DAC A)

(4) 1 IQ pairs

(5) 4 serdes lanes

(6)Interprolation=6

(8)sysref=25MHz, lane rate = 8GHz

(9)FPGA  GTH refclk=200MHz

(11) K=16,RBD=15

QUESTION:

1. We read register  0x64 to 0x67; 

(1)error of 0x2000 will appear between 0x64 to 0x67

2.sync signal

(1)the sync signal is from high to low like the image

3.i try to figure out which link parameter is wrong and the image of link configuration is below

in the second multi-frame, i cannot realize the meaning of data of link parameter,can you give me a hand?

how can i deal with the problem?

Best Regards,

Caps

  • 0
    TI__Mastermind 20541 points

    Hi

    It looks like you are able to complete CGS( code group synchronization). You are getting stuck in ILAS( initial Lane alignment sequence). Here read through the following blog you see the next step in JESD bring up process.

    https://e2e.ti.com/blogs_/b/analogwire/posts/jesd204b-how-to-bring-up-your-link

    Regards,

    Neeraj

  • 0 in reply to Neeraj Gill
    Prodigy 20 points

    Neeraj, Thanks for your response. I check my link parameter in Vivado and the value set in DAC38RF82's register, i don't find any difference.

    Also, i check the required electrical connections between the TX and RX, and i don't find any wrong.

    I have no idea on the sync always from high to low,can you give me any other suggestions?

  • 0 in reply to Tiewei Chen
    TI__Mastermind 20541 points

    Hi,

    One thing to try is reduce the sampling clock by half and then try if you can get the link to establish. If it works at lower SERDES rate than we know it a signal integrity issue.

    Regards,

    Neeraj

  • 0 in reply to Neeraj Gill
    Prodigy 20 points

    Hi Neeraj,

    I have reduced the sampling clock by half and the problem still exist just as i said before.

    what else can i do to solve it?

    i really have no idea on how to solve it.

    Thanks for your help.

  • 0 in reply to Tiewei Chen
    TI__Guru* 91947 points

    Tiewei,

    LMFC period must be longer than the longest link delay. The K parameter (frames/multiframe) determines the LMFC period.

    1 < K < 32

    17 < K*F < 1024

    You cannot use a K = 16 with F =1 per the JESD204B standard. You must meet the equations shown above.  Please try changing the value of K to 20. I ran our hardware with your setup using a value of 20 for K and 19 for RBD. SYSREF was set to 5MHz. The DAC38RF82 and LMK04828 register settings used are attached.

    Regards,

    Jim

    4211_Fs_4800Msps_6x_int.cfg

  • 0 in reply to jim s
    Prodigy 20 points

    Hi Jim,

    Thanks for your reply! I have changed the K parameter from 16 to 32 before your reply and the problem still exist.

    Now I'd like to change the value of K to 20 and check the configuration.

    Regards,

    Tiewei

  • 0 in reply to jim s
    Prodigy 20 points

    Hi Jim,

    I have some questions about the register settings you have attached.

    The value of register 0x14F is 0x1C60, the description of the register is  "Assert if the TX side does not support lane initialization. This way the RX won’t flag errors in the configuration portion of the ILA."

    What's that means?I'm confused.

    Thanks for your help.

    Regards,

    Tiewei

  • 0 in reply to Tiewei Chen
    TI__Guru* 91947 points

    Tiewei,

    This register is set by the load default command and I am not sure who set this value and why. I would suggest using the reset default value of 0x1CC1 for this register.

    Basically, bit 5 is used to bypass the ILA sequence for the DAC. This sequence is not needed. If CGS completes properly and all parameters are set properly for both the TX and RX devices, the link will get established. 

    If bit 5 is set, and the DAC encounters an error, this could cause the DAC to send SYNC back low depending on what error registers are set.

    What is the status of the SYNC signal when you change K = 20?

    Regards,

    Jim  

  • 0 in reply to jim s
    Prodigy 20 points

    Hi Jim,

     Thanks for your timely response.

    (1)I have changed K = 20, but the problem still exist.

    the SYNC signal goes high to low like the image.

    When I use  0x1C60 as the value of register 0x14F. The SYNC signal is always high and I can also transfer data.The DAC has output .

    I can't figure out the reason. Can you give me some advice?

    (2)I have some troubles with NCO

    when I want to use NCO,what register should I change?

    below the sampling rate,I set NCO frequency 80MHz.

    After the start-up sequence, the value of register I have changed:

    0x10C:0x2402 -> 0x2622

    0x11E: 0x0000 -> 0x0444

    0x11F: 0x0000 -> 0x4444

    0x120: 0x0000 -> 0x4444

    0x127: 0x1144 -> 0x8184 (I'm confused about this register)

    The signal has no change.Can you give me some advice?

    Regards,

    Tiewei.

  • 0 in reply to Tiewei Chen
    Prodigy 20 points

    Hi Jim,

    I am also confused of the difference between Mixer and CMix. The data sheet of DAC38RF82 doesn't explain their meanings.

    Thanks for your kind help!

    Regards,

    Tiewei

  • 0 in reply to Tiewei Chen
    TI__Guru* 91947 points

    Tiewei,

    The part has a course mixer and fine mixer. The fine mixer uses the NCO to allow you to shift the spectrum anywhere from 0 to Fs/2.

    The course mixer allows you to shift the spectrum to one of the following locations:

    -Fs/4, Fs/2, Fs/8, 3Fs/8, 5Fs/8 and 7Fs/8. The main reason one would use the course mixer over the fine mixer and NCO is a reduction in power.

    All of this is explained in section 8.3.17.5 of the data sheet.

    Regards,

    Jim

       

  • 0 in reply to jim s
    Prodigy 20 points

    Hi Jim,

    Thanks for your timely response.

    Before the question of Mixer, I don't solve the earlier problem I have met.Just like:

    (1)I have changed K = 20, but the problem still exist.

    the SYNC signal goes high to low like the image.

    But when I use  0x1C60 as the value of register 0x14F. The SYNC signal is always high and I can also transfer data.The DAC has output .

    I can't figure out the reason. 

    Can you give me some advice?

    Regards,

    Tiewei

  • +1 in reply to Tiewei Chen
    TI__Guru* 91947 points

    Tiewei,

    I think the issue is with your FPGA IP. Just use a setting of 0x1C60. Is there a problem with using this setting?

    Regards,

    Jim 

  • 0 in reply to jim s
    Prodigy 20 points

    Hi Jim,

    When I use  0x1C60 as the value of register 0x14F. The SYNC signal is always high and I can also transfer data.The DAC has output .

    I haven't found further problem yet.

    I really appreciate your help these days！

    Regards,

    Tiewei