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Original question:

AFE7444EVM: Setting the right configuration using AFE7444 evaluation GUI

AFE7444EVM: AFE7444

ganesh singh1
Intellectual 400 points

Part Number: AFE7444EVM

Hi ,

I am also trying to do follwing configuration . But the RX side I dont see RX sync Up. Please help

  • 0
    TI__Genius 17891 points

    Hi Ganesh,

    One possible reason that the link is not established is because the FPGA clock may not be set to the proper frequency. Can you verify that the LMK is programmed to generate a 245.76MHz clock?

    When following the steps you mention is the DAC link established?

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Intellectual 400 points

    Hi David,

    Yes, we are trying from EVM  and LMK is giving a clock of 245.76 MHz. We checked that.  We also changed the FPGA ( KCU105) JESD phy rate to 9.8304 Gbps

    DAC Clock( MHz)/ADC clock DAC Sampling rate(GSPS)/ADC Sampling N (TX resolution) in Bits  Interpolation/Decimation JESD204B data Rate(MSPS)  LMFSHd L M F S Data Rate(Gbps) Rate Per serdes (Gbps)
    8847.36 9 16 18 491.52 44210 4 4 2 1 39.3216 9.8304
    2949.12 3 16 6 491.52 44210 4 4 2 1 39.3216 9.8304

    row one is for DAC and Row 2 for ADC.

    Yes TX data was established and DAC gives out data also. Although we have not checked it over a long time. 

    Please let me know the LMFS values are correct or not. 

    With Regards,

    Ganesh Singh

  • 0 in reply to ganesh singh1
    TI__Genius 17891 points

    Hi Ganesh,

    I would suggest verifying that the pin mapping between the AFE7444EVM and KCU105 is correct. If the lane mapping or lane polarity are incorrect then the JESD link would not establish properly.

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Intellectual 400 points

    Hi,

    I run Mode 6 first that was perfect on this mode.

    After that I change the Interpolation and decimation and then its not wokring. 

    So the Setup and pin mapping is correct. 

    Do we need any other lane polarity Chnage in Mode 6 and this mode , Please let us know.

    WIth regards,

    Ganesh Singh

  • 0 in reply to ganesh singh1
    TI__Genius 10865 points

    Hi Ganesh,

    As suggested in the call we had this week, please use TI JESD IP reference design as a starting point and update it for this mode. We can debug if you still face any issues with that. 

    Regards,

    Vijay