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AFE7444EVM: JESD TI IP

ganesh singh1
Intellectual 400 points

Part Number: AFE7444EVM

We are facing issue with the TI jesd IP. We took the design on zcu102 as a reference point and upgraded the design to kcu105. We updated the clock on the transciever to support mode 6 on AFE7444, which is 184.32 MHz., and 32 bits user data width. Please see the attached photo.
The tx side seems to be working smoothly, however the rx side is on reset mode, and no data reaches the FPGA. Rx_sync_n = 1.
Any suggestions from you side?

  • 0
    TI__Genius 17891 points

    Hi Ganesh,

    Are you following the steps mentioned in the TI204c-Setup document to establish the Rx JESD link? When you release the rx_sync_reset_vio do you see rx_lmfc_to_buffer_release_delay update?

    One thing you can try is after releasing the rx_sync_reset toggle the master_reset_n and then attempt to capture data.

    Regards,

    David Chaparro