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AFE7769: RF Synchronisation Problem

tamer gudu
Prodigy 140 points
Part Number: AFE7769
Other Parts Discussed in Thread: AFE7799

Hi Team,

When we use more than one AFE7799 on the same PCB, there may be phase differences between the signals at the RF outputs of these different AFE7799 transceivers due to some uncertainities of the clock distribution network (for example the mismatch between transmission lines distributing LO to the transceivers and this mismatch may be temperature dependent). Do you have any solution for multichip RF synchronization to overcome this problem? By this way we can make sure that the outputs of all transceivers on the PCB will be phase synchronized. If you have a solution, can you please share a block diagram of the recommanded multichip synchronization solution.

Dr. Tamer Güdü

ASELSAN A.S

Turkey

  • 0
    TI__Guru 66004 points

    Hi Dr. Gudu

    I believe our team may have answered this question to you offline. Let me check with the team and get back to you on this. Thank you

    -Kang

  • 0 in reply to Kang Hsia
    TI__Guru 66004 points

    Hi Dr. Gudu,

    Below is a summary of what our system's team may have communicated to you. If you need further discussion, it is best to reach out to the field sales for additional communications and we would be happy to arrange meetings to discuss. The E2E may have limitations in disclosing advanced NDA topics.

    As discussed the antenna calibration is done at system level and it involves the host (FGPA or ASIC) controlling and driving multiple of our devices, sending and receiving test signals and estimating the correction coefficients. Our customers implement their own calibration scheme and we just help with the configuration of our device. Some example involves using the RX chain to calibrate the TX beam forming during RX idle time, and use TX chain to the calibrate the RX beam forming during TX idle time, etc.

    Also the phase/amplitude error among multiple chains is not just determined by the internal LO of the AFE77xx, but it is also created by the LO buffer chains, TX and RX chain (both inside the AFE77xx and outside), etc... What our devices provide through sysref is the ability to have deterministic latency. How to set-up and use sysref is something we can definitively provide and show. How to arrange the calibration circuitry on the board, which signal type to send, how/where to capture the signal, how to measure the error.. is beyond our typical support and of which we (DCC-WI) do not have experience, as this is a system level and software level implementation.