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AFE7444: How to reduce phase noise between different board Loopback test?

Part Number: AFE7444
Other Parts Discussed in Thread: LMK04828

We're testing AFE7444 and got phase jitter issue.

LMK04828 used to offer clock (360MHz) for AFE7444


AFE7444 internal PLL is activated and up-convert frequency to 5760MHz as DAC sampling rate.

As we loop back AFE7444 (RF loop back) on the single board, Phase Jitter is about +/- 0.2 degree. 

As we use AFE7444 on 2 different baord:  AFE7444 on board A as RF TX, while AFE7444 on board B as RF XPhase Jitter rapidly increased to+/- 4degree.

By tuning AFE7444 PLL_register (CP_ADJ Reg), Phase Jitter drop to +/- 3degree, but still far about our goal +/-0.2 degree 

Question (1)  Based on AFE7444 Loopback test result on single board, can we confirm the phase jitter is small due to ADC 's clock and DAC's Clock interaction?

So when AFE7444 got Tx/Rx loopback test under 2 different boards, the phase jitter will become worse as ADC 's Clock /DAC's Clock  are non-correlated (even it's synchronized by LMK04828), right?


Question (2) Do we have solution to tune AFE7444 PLL Phase Jitter performance so phase jitter always as -/+0.2 degree, no matter under single board (RF loop back) test or different board test ? 

  • Hi Andy,

    When the DAC output is looped back to ADC of the same AFE device, as same PLL is generates clock for both DAC and ADC, PLL phase noise gets canceled in the ADC output. That’s why they get small Phase Jitter for this case.

    When DAC output of an AFE is fed to the ADC in another AFE, phase noise of DAC is uncorrelated to the phase noise of ADC. So, in the ADC output, phase noise gets added in power. Only way to improve this is to feed a common external clock to both AFEs bypassing AFE internal PLLs. In this case, an external 5760 MHz should be given as Fref to both AFEs to improve the phase jitter.



  • Vijay, thank you for the reply.