Part Number: AFE7900EVM
Other Parts Discussed in Thread: AFE7900, TI-JESD204-IP
Hello support team,
we are planning to use AFE7900EVM with ZCU102 xilinx evaluation platform board. For AFE7900EVM , I have below list of queries, request you to please guide and support.
Our primary requirements.
ADC sample rate: 500 MSPS
ADC Resolution: 14 bit
Input RF frequency : up to 100 MHz
Simultaneous ADC input channels : quad (4)
1. As our frequency range requirement is lower up to 100 MHz, so AFE7900EVM would be a suitable option. From the AFE7900 datasheet, I have found that there is an ADC sample rate divider (1,2,3,4,6 or 8), i.e. what I understand is that there is an internal ADC clock of 3 GSPS and then I have to use the division of 6 in order to provide 500 MSPS sampling rate to ADC, right?
2. In order to interface the AFE7900EVM to the Xilinx platform(ZCU102), TI-JESD204-IP is there, for which I have requested access. This IP core is free with the purchase of an evaluation board or there is any extra cost for the IP core?
3. The full-scale input power ADC range is given for different combinations of (Input frequency, ADC sample rate, NCO frequency, and Decimation selected). Is there any equation/calculation that needs to be done for defining the full-scale input power ADC range( let's say, Fin= 60 MHz, NCO freq=60 MHz, ADC sample rate=500 MSPS, decimation=16) what will be the full-scale input power ADC range?
4. I assume that the given full-scale input power range is single-ended and baluns are there in evaluation board, right?
5. My dynamic input range is 10mVP-P to 1Vp-p (-36 dBm to 4 dBm), so, I think, I need to use external VGA/DSA to be fall into the ADC input full scale power range? right?
6. With AFE7900EVM and ZCU102 evaluation board procurement, all other supporting resources are freely available or is there any extra cost for any of the resources?
Request for your quick support and guidance to further select the AFE7900EVM.
