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AFE7900EVM: Regarding Latte python based script tool

Maitry Khambhati
Intellectual 450 points
Part Number: AFE7900EVM


Hello support Team,

As I have gone through the Latte python based scripting tool as well schematic of the AFE7900EVM , I realize that there are some of the GPIO pins available which are not fixed as well defined. So, Based on our own requirement, we can utilize these GPIO pins to generate new functions using Latte python scripting , right?

If yes, then below is my planning to utilize available non-defined GPIO pins , please verify weather we can do like this or any other way you can suggest?

1) Continuous calculation of DDC FFT output by development of python script in Latte and assign that to any GPIO pin so that from that GPIO pin, Based on that implementation, we can continuous read the difference of Input RF frequency and NCO frequency using GPIO pin.

2) Assign current DSA value and External LNA gain value to GPIO pins using Latte python script so that we can read continuously from the GPIO pin.

Like this, We can utilize available GPIO pins to read back some of the details as per above example given. Please suggest and verify. 

  • 0
    TI__Intellectual 1180 points

    Hi Maitry,

    I am regrettably unable to provide detailed answers for any of your questions at this time, but our AFE experts will address your question as soon as they are able. Please be patient as they are still out of the office until Monday.

    Thanks,

    Drew

  • 0 in reply to Drew Pierpont
    Intellectual 450 points

    Hi Drew,

    I am hoping to receive the answers of my raised queries in this week as early as possible. Request you to please look in to the raised queries to provide guidance and support as it has been pending from last week.

  • 0 in reply to Maitry Khambhati
    TI__Mastermind 18041 points

    Hi Maitry,

    One thing to note about the GPIO pins is that there are defined functions that the GPIO pins can be used for, the datasheet covers the functions available. Unfortunately there is no option to create custom functions for the GPIO pins, such as reading back the DSA value on a GPIO pin. 

    The continuous calculation of the FFT will have to take place inside the FPGA. Once you know the difference in frequency you can update the NCO using SPI writes or the GPIO pins. The AFE does not have a feature to perform a FFT and the Latte software is only used to program the AFE.

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Intellectual 450 points

    Hi David,

    Thanks for the Clarification.

    As per table 8-21 given in the datasheet, there are total 40 GPIO pins are utilized for the default functions and for the other available functions, total 59 GPIO pins are dedicated to the other available functions. As some GPIO pins can be used as a multi-function pin. Based on our requirement , we can utilize the GPIO pins.

    Out of all the available GPIO functions, I don't understand the GPIO pins assignment to external DVGA control. For total 4 input RF-ADC channels, there will be total 4 external DVGA. In order to control 4 different External DVGA simultaneously for all 4 channels, the available GPIO functions are only 6. then, can you please elaborate how to control 4 simultaneous External DVGA using internal AGC mechanism via GPIO functions?

  • 0 in reply to Maitry Khambhati
    TI__Mastermind 18041 points

    Hi Maitry,

    This question was answered in a separate e2e question, https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1111753/afe7900evm-regarding-internal-agc-configuration-in-afe7900evm/.

    Here is the answer provided in the other post: The DVGA related information in the configuration guide is copied over from legacy documentation. Internal AGC only supports an LNA bypass feature with one pin control (for each Receive channel). DVGA control is not supported by internal AGC. If an application must need an external DVGA, External AGC mode should be used. In this case, DVGA and DSA attenuation should be controlled by the FPGA. 

    Regards,

    David Chaparro